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US 11,056,167 B2Granted
Apparatuses for refreshing memory of a semiconductor device
AssigneeMicron Technology, Inc.
InventorsYutaka Ito, Yoshifumi Mochida, Hiroei Araki
Life of this patent
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Abstract
Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
Claims6
A method, comprising:
- updating a refresh address responsive to a refresh command;
- refreshing memory for the refresh address when the refresh address is directed to a regular array;
- skipping refresh of memory for the refresh address in the regular array when the refresh address is directed to a redundant array;
- refreshing memory of the redundant array to which the refresh address is directed;
- and
- generating a row hammer refresh address, interrupting the refreshing of the regular array and performing a refresh operation on the row hammer refresh address.
3 more elements
Dependencies are inferred from the claim text.