Memory device and divided clock correction method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Seok Kang, Seungjun Bae
Life of this patent
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Abstract
A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.
Claims13
A memory device comprising:
- an internal clock generator that is configured to generate a plurality of internal clock signals by dividing a received clock signal, where each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals;
- a serializer that is configured to use the internal clock signals to serialize training data;
- a data output buffer that is configured to output the serialized training data;
- and
- a clock controller that is configured to correct a clock dividing start time point of the received clock signal based on a control signal provided by a host,
- wherein a value of the control signal is based on a time that the serialized training data was received at the host.
A method for correcting a clock dividing start time point of a memory device, the method comprising:
- sampling serial test data that is received from a host using a plurality of internal clock signals to deserialize the serial test data, wherein the serial test data is sampled using one of a rising edge or a falling edge of each of the internal clock signals;
- and
- configuring the memory device to sample data that is received from the host using an other one of the rising edge or the falling edge of each of the internal clock signals responsive to a determination that the deserialized serial test data was deserialized out of order.
A method for correcting a clock dividing start time point of a memory device, the method comprising:
- serializing test data to provide a serialized data pattern using a plurality of internal clock signals that are generated by dividing a clock signal that is received from the host;
- comparing reference data with the serialized data pattern;
- and
- correcting the clock dividing start time point of the clock signal based on the comparison of the reference data with the serialized data pattern.
Dependencies are inferred from the claim text.