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US 11,056,154 B2Granted
Semiconductor memory device
AssigneeWinbond Electronics Corp.
InventorSho Okabe
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device for reducing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.
Claims19
A semiconductor memory device, comprising:
- a memory cell array in a chip;
- a plurality of charge pump circuits, arranged in the chip;
- and
- a controller, arranged in the chip and controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing,
- wherein each of the plurality of charge pump circuits comprise:
- a pump circuit;
- a generation circuit receiving a clock signal to generate a first clock signal and a fourth clock signal;
- a first inverter receiving and inverting the first clock signal to generate a second clock signal;
- and
- a second inverter receiving and inverting the fourth clock signal to generate a third clock signal,
- wherein the first, second, third, and fourth clock signals are provided to the pump circuit.
8 more elements
A semiconductor memory device, comprising:
- a memory cell array in a chip;
- a plurality of charge pump circuits, arranged in the chip;
- and
- a controller, arranged in the chip and controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing,
- wherein the controller controls the timing of activating the charge pump circuits when performing reading during a bit line precharge period.
2 more elements
Dependencies are inferred from the claim text.