High-voltage unity-gain buffer
AssigneeAnalog Devices International Unlimited Company
InventorsRoderick McLachlan, Fergus Downey
Life of this patent
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Abstract
Described are various techniques that can minimize the use of high-voltage devices in a unity-gain buffer that can be used in a high voltage application, while providing a circuit that generates an output that is an accurately buffered version of the input.
Claims34
A circuit for use with high voltage supply nodes, wherein voltages of the high voltage supply nodes are large enough to exceed a voltage capability of a low voltage transistor structure in the circuit but not large enough to exceed a high voltage capability of a high voltage transistor structure in the circuit, voltages of low voltage supply nodes are low enough to accommodate a voltage capability of a low voltage transistor structure in the circuit, the low voltage supply nodes derived from the high voltage supply nodes, the low voltage supply nodes including a low voltage upper rail and a low voltage lower rail, the high voltage supply nodes including a high voltage upper rail and a high voltage lower rail, the circuit comprising:
- a buffer circuit for providing a gain to an input signal applied thereto, the buffer circuit including:
- an output transistor circuit;
- and
- a low voltage circuit coupled between the high voltage supply nodes and to the low voltage upper and lower rails, wherein the low voltage upper and lower rails are biased with respect to a voltage level of the input signal, the low voltage circuit including:
- a differential stage configured to receive the input signal and a representation of an output of the buffer circuit,
- wherein the output transistor circuit is coupled to an output of the differential stage and configured to provide the output of the buffer circuit.
A buffer circuit for providing a gain to an input signal applied thereto and for use with high voltage supply nodes, wherein voltages of the high voltage supply nodes are large enough to exceed a voltage capability of a low voltage transistor structure in the circuit but not large enough to exceed a high voltage capability of a high voltage transistor structure in the circuit, voltages of low voltage supply nodes are low enough to accommodate a voltage capability of a low voltage transistor structure in the circuit, the low voltage supply nodes derived from the high voltage supply nodes, the low voltage supply nodes including a low voltage upper rail and a low voltage lower rail, the high supply voltage supply nodes including a high voltage upper rail and a high voltage lower rail, the buffer circuit comprising:
- an output transistor circuit;
- and
- a low voltage circuit coupled between the high voltage supply nodes and to the low voltage upper and lower rails, wherein the low voltage upper and lower rails are biased with respect to a voltage level of the input signal, the low voltage circuit including:
- a differential stage configured to receive the input signal and a representation of an output of the buffer circuit,
- wherein the output transistor circuit is coupled to an output of the differential stage and configured to provide the output of the buffer circuit.
A method for operating a buffer circuit configured to provide a gain to an input signal applied thereto and for use with high voltage supply nodes, wherein voltages of the high voltage supply nodes are large enough to exceed a voltage capability of a low voltage transistor structure in the circuit but not large enough to exceed a high voltage capability of a high voltage transistor structure in the circuit, voltages of low voltage supply nodes are low enough to accommodate a voltage capability of a low voltage transistor structure in a circuit, the low voltage supply nodes derived from the high voltage supply nodes, the low voltage supply nodes including a low voltage upper rail and a low voltage lower rail, the high voltage supply nodes including a high voltage upper rail and a high voltage lower rail, the method comprising:
- coupling a low voltage circuit between the high voltage supply nodes and to the low voltage upper and lower rails, wherein the low voltage upper and lower rails are biased with respect to a voltage level as the input signal, the low voltage circuit including a differential stage having a first input and a second input;
- receiving the input signal using the first input and receiving a representation of an output of the buffer circuit using the second input;
- coupling an output transistor circuit to an output of the differential stage;
- and
- providing, using the output transistor circuit, the output of the buffer circuit.
A circuit for use with high voltage supply nodes, wherein voltages of the high voltage supply nodes are large enough to exceed a voltage capability of a low voltage transistor structure in the circuit but not large enough to exceed a voltage capability of a high voltage transistor structure in the circuit, and voltages of low voltage supply nodes are low enough to accommodate a voltage capability of a low voltage transistor structure in the circuit, the circuit comprising:
- a buffer circuit for providing substantially unity gain to an input signal applied thereto, the buffer including:
- a current source with high-voltage capability configured to couple to a first high voltage supply node;
- a current sink with high-voltage capability configured to couple to a second high voltage supply node;
- a low voltage circuit coupled to low voltage supply nodes between the current source and the current sink, the low voltage circuit including:
- a differential stage having a first input and a second input, the first input configured to receive the input signal and the second input configured to receive a representation of an output of the buffer circuit;
- and
- an output transistor circuit connected in a follower configuration and coupled to the output of the differential stage, the output transistor circuit configured to provide the output voltage of the buffer circuit.
Dependencies are inferred from the claim text.