# US 11,050,397 B2 · Interpolation operational amplifier circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,050,397 B2 - Document ID: US11050397B2 - Status: Granted - Kind: B2 - Application number: 16/875,342 - Filed: 2020-05-15 - Published: 2021-04-15 - Granted: 2021-06-29 - Earliest claimed: 2019-10-15 - Assignees: Seeya Optronics Co., Ltd. - Applicants: Shanghai Seeo Optronics Technology Co., Ltd - Inventors: Ping-Lin Liu; Haodong Zhang - Web page: https://patentgrep.com/patent/US11050397B2 ## CPC - H03F 3/4521: {Complementary long tailed pairs having parallel inputs and being supplied in parallel} - H03F 3/45219: {Folded cascode stages} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - H03F 3/3066: {the collectors of complementary power transistors being connected to the output} - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - H03F 2203/45144: At least one follower being added at the input of a dif amp - H03F 2203/45508: the CSC comprising a voltage generating circuit as bias circuit for the CSC - H03F: AMPLIFIERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Provided is an interpolation operational amplifier circuit, including: at least two sets of differential input pair transistors, each differential input pair transistor including first and second transistors, wherein base terminals of the first and second transistors are electrically connected to serve as a base terminal of the differential input pair transistor, and source electrodes of the first and second transistors are electrically connected to serve as a source electrode of the differential input pair transistor; and a voltage control unit electrically connected to the base terminal and source electrode of the differential input pair transistor, and configured to control a voltage of the base terminal of the P-type differential input pair transistor to be smaller than the first power supply voltage, and/or to control a voltage of the base terminal of the N-type differential input pair transistor to be larger than the second power supply voltage. ## Claims ### Claim 1 An interpolation operational amplifier circuit, comprising: a first power supply input terminal and a second power supply input terminal, wherein a first power supply voltage of the first power supply input terminal is larger than a second power supply voltage of the second power supply input terminal; at least two sets of differential input pair transistors, each set of differential input pair transistors comprising a P-type differential input pair transistor composed of P-type transistors and an N-type differential input pair transistor composed of N-type transistors, wherein each differential input pair transistor of the at least two sets of differential input pair transistors comprises a first transistor and a second transistor, a gate electrode of the first transistor of at least one set of the at least two sets of differential input pair transistors is electrically connected to a first input terminal of the interpolation operational amplifier circuit, and a gate electrode of the first transistor of at least another set of the at least two sets of differential input pair transistors is electrically connected to a second input terminal of the interpolation operational amplifier circuit; for each differential input pair transistor of the at least two sets of differential input pair transistors, body terminals of the first transistor and the second transistor of the differential input pair transistor are electrically connected to each other to serve as a body terminal of the differential input pair transistor, and source electrodes of the first transistor and the second transistor of the differential input pair transistor are electrically connected to each other to serve as a source electrode of the differential input pair transistor; and voltage control units each electrically connected to the body terminal of the differential input pair transistor and the source electrode of the differential input pair transistor, and configured to control a voltage of the body terminal of the P-type differential input pair transistor to be smaller than the first power supply voltage of the first power supply input terminal, and/or to control a voltage of the body terminal of the N-type differential input pair transistor to be larger than the second power supply voltage of the second power supply input terminal. ### Claim 2 (depends on 1) The interpolation operational amplifier circuit according to claim 1, wherein each of the voltage control units comprises a conductive wire, and the conductive wire is electrically connected to the body terminal and the source electrode of the differential input pair transistor. ### Claim 3 (depends on 1) The interpolation operational amplifier circuit according to claim 1, wherein each of the voltage control units comprises a first voltage input terminal; the first voltage input terminal is electrically connected to the body terminal of the differential input pair transistor, so as to provide a first voltage to the body terminal of the differential input pair transistor; the first voltage is smaller than a voltage of the source electrode of the P-type differential input pair transistor, and the first voltage is larger than a voltage of the source electrode of the N-type differential input pair transistor. ### Claim 4 (depends on 3) The interpolation operational amplifier circuit according to claim 3, wherein a difference between the first voltage and the voltage of the source electrode of the differential input pair transistor is smaller than a PN junction forward turn-on voltage between the body terminal and the source electrode of the differential input pair transistor. ### Claim 5 (depends on 3) The interpolation operational amplifier circuit according to claim 3, wherein each of the voltage control units further comprises at least one first source follower; each of the at least one first source follower comprises an input terminal electrically connected to the source electrode of the differential input pair transistor, and an output terminal electrically connected to the body terminal of the differential input pair transistor. ### Claim 6 (depends on 5) The interpolation operational amplifier circuit according to claim 5, wherein a turn-on voltage of the at least one first source follower is smaller than a turn-on voltage between the body terminal and the source electrode of the differential input pair transistor. ### Claim 7 (depends on 5) The interpolation operational amplifier circuit according to claim 5, wherein each of the at least one first source follower is a PMOS transistor or an NMOS transistor; the P-type differential input pair transistor is electrically connected to the NMOS transistor, and the N-type differential input pair transistor is electrically connected to the PMOS transistor; each of the PMOS transistor and the NMOS transistor comprises: a gate electrode that is the input terminal of one of the at least one first source follower, and a source electrode that is an output terminal of one of the at least one first source follower; the PMOS transistor further comprises a drain electrode electrically connected to the second power supply input terminal, and the NMOS transistor further comprises a drain electrode electrically connected to the first power supply input terminal. ### Claim 8 (depends on 7) The interpolation operational amplifier circuit according to claim 7, wherein one of the voltage control units further comprises a second voltage input terminal, and another one of the voltage control units further comprises a third voltage input terminal; the second voltage input terminal is electrically connected to a body terminal of the PMOS transistor, so as to provide a second voltage to the body terminal of the PMOS transistor; the third voltage input is electrically connected to a body terminal of the NMOS transistor, so as to provide a third voltage to the body terminal of the NMOS transistor; the second voltage is smaller than a voltage of the source electrode of the PMOS transistor, and the third voltage is larger than a voltage of the source electrode of the NMOS transistor. ### Claim 9 (depends on 8) The interpolation operational amplifier circuit according to claim 8, wherein the voltage control units further comprise at least two second source followers, the at least two second source followers comprise: at least one second source follower comprising an input terminal electrically connected to the source electrode of the PMOS transistor, and an output terminal electrically connected to the body terminal of the PMOS transistor; and at least one second source follower comprising an input terminal electrically connected to the second power supply input terminal, and an output terminal electrically connected to the body terminal of the NMOS transistor. ### Claim 10 (depends on 7) The interpolation operational amplifier circuit according to claim 7, wherein the voltage control units further comprise at least one current source connected in series between the body terminal of the PMOS transistor and the source electrode of the PMOS transistor and/or connected in series between the body terminal of the NMOS transistor and the second power supply input terminal. ### Claim 11 (depends on 1) The interpolation operational amplifier circuit according to claim 1, wherein the at least two sets of differential input pair transistors comprise four differential input pair transistors forming a differential stage amplifier circuit of the interpolation operational amplifier circuit, the four differential input pair transistors comprising a first differential input pair transistor, a second differential input pair transistor, a third differential input pair transistor and a fourth differential input pair transistor; the gate electrode of the first transistor of the first differential input pair transistor and the gate electrode of the first transistor of the third differential input pair transistor are electrically connected to the first input terminal of the interpolation operational amplifier circuit, and the gate electrode of the first transistor of the second differential input pair transistor and the gate electrode of the first transistor of the fourth differential input pair transistor are electrically connected to the second input terminal of the interpolation operational amplifier circuit; the gate electrodes of the second transistors of the four differential input pair transistors are electrically connected to an output terminal of the interpolation operational amplifier circuit; a drain electrode of the first transistor of the first differential input pair transistor and a drain electrode of the first transistor of the second differential input pair transistor are electrically connected to a first output terminal of the differential stage amplifier circuit, and a drain electrode of the second transistor of the first differential input pair transistor and a drain electrode of the second transistor of the second differential input pair transistor are electrically connected to a second output terminal of the differential stage amplifier circuit; the source electrodes of the first differential input pair transistor and the second differential input pair transistor are electrically connected to a negative terminal of a first current source; a positive terminal of the first current source, and body terminals of the first differential input pair transistor and the second differential input pair transistor are electrically connected to the first power supply input terminal of the interpolation operational amplifier circuit; the gate electrodes of the second transistors of the third differential input pair transistor and the fourth differential input pair transistor are electrically connected to the output terminal of the interpolation operational amplifier circuit; a drain electrode of the first transistor of the third differential input pair transistor and a drain electrode of the first transistor of the fourth differential input pair transistor are electrically connected to a third output terminal of the differential stage amplifier circuit; a drain electrode of the second transistor of the third differential input pair transistor and a drain electrode of the second transistor of the fourth differential input pair transistor are electrically connected to a fourth output terminal of the differential stage amplifier circuit; the source electrodes of the third differential input pair transistor and the fourth differential input pair transistor are electrically connected to a positive terminal of a second current source; a negative terminal of the second current source, and the body terminals of the third differential input pair transistor and the fourth differential input pair transistor are electrically connected to the second power supply input terminal of the interpolation operational amplifier circuit. ### Claim 12 (depends on 11) The interpolation operational amplifier circuit according to claim 11, wherein the first transistor of the first differential input pair transistor, the second transistor of the first differential input pair transistor, the first transistor of the second differential input pair transistor, and the second transistor of the second differential input pair transistor are PMOS transistors; and the first transistor of the third differential input pair transistor, the second transistor of the third differential input pair transistor, the first transistor of the fourth differential input pair transistor, and the second transistor of the fourth differential input pair transistor are NMOS transistors. ### Claim 13 (depends on 11) The interpolation operational amplifier circuit according to claim 11, further comprising an intermediate stage amplifier circuit and an output stage amplifier circuit, the differential stage amplifier circuit comprises: the first output terminal electrically connected to a first input terminal of the intermediate stage amplifier circuit, the second output terminal electrically connected to a second input terminal of the intermediate stage amplifier circuit, the third output terminal electrically connected to a third input terminal of the intermediate stage amplifier circuit, and the fourth output terminal electrically connected to a fourth input terminal of the intermediate stage amplifier circuit; the intermediate stage amplifier circuit comprises a first output terminal electrically connected to a first input terminal of the output stage amplifier circuit, and a second output terminal electrically connected to a second input terminal of the output stage amplifier circuit; and output stage amplifier circuit comprises an output terminal that is the output terminal of the interpolation operational amplifier circuit.