Long channel nanosheet FET having tri-layer spacers

A semiconductor device comprising:

• a plurality of vertically aligned long channel semiconductor channel layers disposed above a substrate layer;
• a plurality of vertically aligned short channel semiconductor channel layers disposed above the substrate layer;
• a plurality of tri-layer dielectric spacers disposed between the vertically aligned long channel semiconductor layers, wherein the tri-layer dielectric spacers are not disposed between the short channel semiconductor channel layers;
• a gate stack formed on, and around the vertically aligned semiconductor channel layers;
• source and drain elements disposed in contact with sidewalls of the vertically aligned semiconductor channel layers;
• and
• wherein the long channel semiconductor layers comprise a first width and the tri-layer dielectric spacers comprise a second width, the second width being less than the first width.