Signal processing apparatus, signal processing method, program, and signal transmission system

A signal processing method, comprising:

• mapping an 8K video signal or a 4K video signal onto first data streams of respective channels;
• generating, by processing circuitry of a signal processing apparatus, scrambled data blocks by scrambling each one of read data blocks read from a first subset of the first data streams;
• generating, by the processing circuitry of the signal processing apparatus, first data blocks by inverting polarity of every other block of the scrambled data blocks;
• generating, by the processing circuitry of the signal processing apparatus, second data blocks by 8B/10B-converting a second subset of the first data streams that is different from the first subset of the first data streams;
• and
• generating, by the processing circuitry of the signal processing apparatus, second data streams of a plurality of lanes by multiplexing the first data blocks and the second data blocks,
• wherein
• the processing circuitry includes multiplexers for the lanes of the second data streams, respectively,
• each of the multiplexers includes:
• a plurality of first signal processors configured to generate a portion of the first data blocks;
• a plurality of second signal processors configured to generate a portion of the second data blocks;
• a data stream generator configured to generate a corresponding third data stream according to a predetermined word length by multiplexing the portion of the first data blocks and the portion of the second data blocks in a predetermined sequence;
• and
• a parallel/serial converter configured to generate one of the second data streams by parallel/serial-converting the corresponding third data stream, and
• the method further comprises:
• causing the first signal processors and the second signal processors to operate in synchronism with a clock signal of 148.5 MHz or 148.5/1.001 MHz, and output data of a total of 640 bits per every four clock pulses;
• and
• causing the data stream generator to operate in synchronism with a clock signal of x MHz, and outputs data of 180 bits×148.5 MHz÷x MHz (bits) or 180 bits×148.5/1.001 MHz÷(x/1.001) MHz (bits) per clock pulse.

A non-transitory computer-readable medium storing instructions which when executed by a computer cause the computer to perform a process comprising:

• mapping an 8K video signal or a 4K video signal onto first data streams of respective channels;
• generating, by operation of processing circuitry of the computer, scrambled data blocks by scrambling each one of read data blocks read from a first subset of the first data streams;
• generating, by the operation of the processing circuitry of the computer, first data blocks by inverting polarity of every other block of the scrambled data blocks;
• generating, by the operation of the processing circuitry of the computer, second data blocks by 8B/10B-converting a second subset of the first data streams that is different from the first subset of the first data streams;
• and
• generating, by the operation of the processing circuitry of the computer, second data streams of a plurality of lanes by multiplexing the first data blocks and the second data blocks,
• wherein
• the processing circuitry includes multiplexers for the lanes of the second data streams, respectively,
• each of the multiplexers includes:
• a plurality of first signal processors configured to generate a portion of the first data blocks;
• a plurality of second signal processors configured to generate a portion of the second data blocks;
• a data stream generator configured to generate a corresponding third data stream according to a predetermined word length by multiplexing the portion of the first data blocks and the portion of the second data blocks in a predetermined sequence;
• and
• a parallel/serial converter configured to generate one of the second data streams by parallel/serial-converting the corresponding third data stream, and
• the process further comprises:
• causing the first signal processors and the second signal processors to operate in synchronism with a clock signal of 148.5 MHz or 148.5/1.001 MHz, and output data of a total of 640 bits per every four clock pulses;
• and
• causing the data stream generator to operate in synchronism with a clock signal of x MHz, and outputs data of 180 bits×148.5 MHz÷x MHz (bits) or 180 bits×148.5/1.001 MHz÷(x/1.001) MHz (bits) per clock pulse.

A signal transmission system comprising:

• a transmission apparatus that includes first processing circuitry configured to:
• map an 8K video signal or a 4K video signal onto first data streams of respective channels;
• generate scrambled data blocks by scrambling each one of read data blocks read from a first subset of the first data streams;
• generate first data blocks by inverting polarity of every other block of the scrambled data blocks;
• generate second data blocks by 8B/10B-converting a second subset of the first data streams that is different from the first subset of the first data streams;
• generate second data streams of a plurality of lanes by multiplexing the first data blocks and the second data blocks;
• and
• control transmission of the second data streams of the plurality of lanes;
• and
• a reception apparatus that includes second processing circuitry configured to:
• control reception of the second data streams of the plurality of lanes;
• reproduce the first data streams from the second data streams;
• and
• reproduce the 8K video signal or the 4K video signal from the reproduced first data streams,
• wherein
• the first processing circuitry of the transmission apparatus includes multiplexers for the lanes of the second data streams, respectively,
• each of the multiplexers includes:
• a plurality of first signal processors configured to generate a portion of the first data blocks;
• a plurality of second signal processors configured to generate a portion of the second data blocks;
• a data stream generator configured to generate a corresponding third data stream according to a predetermined word length by multiplexing the portion of the first data blocks and the portion of the second data blocks in a predetermined sequence;
• and
• a parallel/serial converter configured to generate one of the second data streams by parallel/serial-converting the corresponding third data stream,
• the first signal processors and the second signal processors operate in synchronism with a clock signal of 148.5 MHz or 148.5/1.001 MHz, and output data of a total of 640 bits per every four clock pulses, and
• the data stream generator operates in synchronism with a clock signal of x MHz, and outputs data of 180 bits×148.5 MHz÷x MHz (bits) or 180 bits×148.5/1.001 MHz÷(x/1.001) MHz (bits) per clock pulse.