Bandwidth enhanced amplifier for high frequency CML to CMOS conversion
AssigneeQUALCOMM Incorporated
InventorsSuresh Naidu Lekkala, Sajin Mohamad
Life of this patent
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Abstract
A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.
Claims20
A current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter, comprising:
- a differential amplifier having
- a first and a second input transistors,
- a first and a second load transistors, wherein the first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor,
- a first transistor coupled in parallel with the first load transistor, and
- a resistor having a first and a second terminals;
- and
- a first capacitor coupled directly between a gate of the first input transistor and a gate of the first load transistor, the first terminal of the resistor coupled to a gate of the first transistor and the second terminal of the resistor coupled to the gate of the first load transistor and the first capacitor.
A system on chip (SoC), comprising:
- a phase interpolator to adjust a phase of an input clock;
- and
- a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter coupled to the phase interpolator to receive output signals from the phase interpolator,
- a differential amplifier having
- a first and a second input transistors,
- a first and a second load transistors, wherein the first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor,
- a first transistor coupled in parallel with the first load transistor, and
- a resistor having a first and a second terminals;
- and
- a first capacitor coupled directly between a gate of the first input transistor and a gate of the first load transistor, the first terminal of the resistor coupled to a gate of the first transistor and the second terminal of the resistor coupled to the gate of the first load transistor and the first capacitor.
A method to convert signals from a current mode logic (CML) circuit to signals usable by complementary metal oxide semiconductor (CMOS) based circuit, the method comprising:
- providing a first and a second input transistors to receive a pair of differential signals from the CML circuit at gates of the first and the second input transistors, and
- coupling a first load transistor in series with the first input transistor;
- coupling a second load transistor in series with the second input transistor;
- coupling a first transistor in parallel with the first load transistor;
- and
- providing a first feed forward path from the first input transistor through the first load transistor, and a second feed forward path from the second input transistor through the second load transistor at high frequency, wherein providing the first feed forward path comprises
- coupling a first capacitor directly between the gate of the first input transistor and a gate of the first load transistor, and
- coupling a resistor between the gate of the first load transistor and a gate of the first transistor.
Dependencies are inferred from the claim text.