Fabrication of vertical fin transistor with multiple threshold voltages

A method of fabricating one or more vertical fin field effect transistors, comprising:

• epitaxially growing a silicon-germanium vertical fin on a single-crystal silicon substrate;
• forming a bottom spacer on the substrate adjacent to the silicon-germanium vertical fin;
• forming a cap on a top surface of the silicon-germanium vertical fin, wherein sidewalls of the silicon-germanium vertical fin are exposed between the cap and the top surface of the bottom spacer layer;
• oxidizing the sidewalls of the silicon-germanium vertical fin to form silicon oxide layers at least on opposite sides of the silicon-germanium vertical fin, and increasing the germanium concentration of the silicon-germanium vertical fin, wherein an area between the cap and the top surface of the silicon-germanium vertical fin is free of the silicon oxide layers;
• removing the silicon oxide layers to form a portion of the silicon-germanium vertical fin having a reduced width, while maintaining the original height of the silicon-germanium vertical fin;
• forming a gate dielectric layer and a gate conductor layer on the silicon-germanium vertical fin having the reduced width, where the gate dielectric layer and a gate conductor layer surround the vertical fin having the reduced width;
• and
• forming a source/drain in the substrate below the silicon-germanium vertical fin.

A method of fabricating one or more vertical fin field effect transistors, comprising:

• epitaxially growing a silicon-germanium vertical fin on a single-crystal silicon substrate;
• forming a cap on a top surface of the silicon-germanium vertical fin;
• forming a bottom spacer on the substrate adjacent to the silicon-germanium vertical fin, wherein the bottom spacer has a height less than the height of the silicon-germanium vertical fin that covers a lower portion of sidewalls of the silicon-germanium vertical fin;
• oxidizing an exposed portion of the sidewalls of the silicon-germanium vertical fin between the bottom spacer and the cap to form silicon oxide layers at least on opposite sides of the silicon-germanium vertical fin, and increasing the germanium concentration of the silicon-germanium vertical fin;
• and
• removing the silicon oxide layers to form an upper portion of the silicon-germanium vertical fin having a reduced width;
• forming a gate dielectric layer and a gate conductor layer on the silicon-germanium vertical fin having a reduced width;
• forming a source/drain in the substrate below the silicon-germanium vertical fin with the reduced width;
• removing the cap to expose the top surface of the silicon-germanium vertical fin with the reduced width;
• and
• forming a source/drain region on the top surface of the silicon-germanium vertical fin with the reduced width.