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US 11,031,917 B2Granted
Method for generating a bias current for biasing a differential pair of transistors and corresponding integrated circuit
AssigneeSTMicroelectronics (Rousset) SAS
InventorsVincent Binet, Yohan Joly
Life of this patent
Estimating the term…
Abstract
An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
Claims26
A method for generating a bias current for biasing a differential pair of transistors which include a first input, a second input, a first intermediate output, a second intermediate output, the method comprising:
- generating a bias current for biasing the first intermediate output and the second intermediate output;
- generating a control voltage arising from a difference in potentials between a potential on the first input and a potential on a node receiving the bias current;
- and
- generating in response to the control voltage an additional current that is added to the bias current.
1 more element
A method for generating a bias current for biasing a differential pair of transistors which include a first input, a second input, a first intermediate output, and a second intermediate output, the method comprising:
- generating a bias current for biasing the first intermediate output and the second intermediate output;
- generating a control voltage arising from a difference in potentials between the first input and the second input by amplifying a difference signal resulting from a difference between the potential on the first input and the potential on the second input;
- and
- generating in response to the control voltage an additional current that is added to the bias current;
- wherein generating the control voltage comprises:
- generating a first control voltage arising from a positive difference in potentials between the first input and the second input, and
- generating a second control voltage arising from a negative difference in potentials between the first input and the second input, and
- wherein generating the additional current comprises:
- generating in response to the first control voltage a first additional current being added to the bias current, and
- generating in response to the second control voltage a second additional current that is added to the bias current.
7 more elements
An integrated circuit, comprising:
- a differential pair of transistors including a first input, a second input, a first intermediate output, a second intermediate output;
- a bias current generator configured to generate a bias current for biasing the first intermediate output and the second intermediate output;
- and
- a control loop configured to generate a control voltage arising from a difference in potentials between a potential on the first input and a potential on a node that is configured to receive the bias current, and to generate in response to the control voltage an additional current that is added to the bias current for biasing the first intermediate output and the second intermediate output.
1 more element
An integrated circuit, comprising:
- a differential pair of transistors including a first input, a second input, a first intermediate output, a second intermediate output;
- a bias current generator configured to generate a bias current for biasing the first intermediate output and the second intermediate output;
- a control loop configured to generate a control voltage arising from a difference in potentials between the first input and the second input, and to generate in response to the control voltage an additional current that is added to the bias current for biasing the first intermediate output and the second intermediate output;
- wherein the control loop comprises an amplifier configured to determine a difference between a potential on the first input and a potential on the second input, and to amplify a signal resulting from the difference so as to generate said control voltage;
- and
- wherein said control loop is configured to generate, as said control voltage, a first control voltage arising from a positive difference in potentials between the first input and the second input and a second control voltage arising from a negative difference in potentials between the first input and the second input, and to generate, as said additional current, a first additional current that is added to the bias current, which generation is controlled by the first control voltage, and a second additional current that is added to the bias current, which generation is controlled by the second control voltage.
3 more elements
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a second differential pair of transistors including a third input, a fourth input, and a second common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- a transistor configured to generate a second bias current for application to the common source bias node;
- an amplifier circuit having a first input configured to receive a voltage at the first input and a second input configured to receive a voltage at the second input, the amplifier circuit configured to determine a difference between the voltage at the first and second inputs and output a control voltage for application to a control terminal of said transistor;
- and
- a switched circuit configured to selectively apply the first and second bias currents to the second common source bias node in response to a control signal.
4 more elements
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- a first transistor configured to generate a second bias current for application to the common source bias node;
- a second transistor configured to generate a third bias current for application to the common source bias node;
- and
- an amplifier circuit having a first input configured to receive a voltage at the first input and a second input configured to receive a voltage at the second input, the amplifier circuit configured to determine a difference between the voltage at the first and second inputs and output a differential control voltage having a first control voltage for application to a control terminal of said first transistor and a second control voltage for application to a control terminal of said second transistor.
3 more elements
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a second differential pair of transistors including a third input, a fourth input, and a second common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- a transistor having a gate node connected to the first input and a source node connected to the common source bias node, wherein a second bias current is generated at the source node for application to the common source bias node;
- and
- a switched circuit configured to selectively apply the first and second bias currents to the second common source bias node in response to a control signal.
3 more elements
Dependencies are inferred from the claim text.