# US 11,031,492 B2 · Semiconductor structure comprising III-N material

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- Number: US 11,031,492 B2
- Document ID: US11031492B2
- Status: Granted
- Kind: B2
- Application number: 16/091,478
- Filed: 2017-03-01
- Published: 2020-06-11
- Granted: 2021-06-08
- Earliest claimed: 2016-04-05
- Assignees: Exagan
- Applicants: Exagan
- Inventors: David Schenk; Alexis Bavard
- Web page: https://patentgrep.com/patent/US11031492B2

## CPC

- H10D 30/4732: {using Group III-V semiconductor material}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/815: of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2926: {Crystal orientations}
- H10P 14/3214: {being Group IIIA-VA semiconductors}
- H10P 14/3216: {Nitrides}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3416: {Nitrides}
- H10P 14/3444: {P-type}
- H10P 14/3446: {Transition metal elements; Rare earth elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure comprising III-N materials, includes: a support substrate; a main layer of III-N material, the main layer comprising a first section disposed on the support substrate and a second section disposed on the first section; an inter-layer of III-N material, disposed between the first section and the second section in order to compress the second section of the main layer, wherein the structure's inter-layer consists of a lower layer disposed on the first section and an upper layer disposed on the lower layer and formed by a superlattice.

## Claims

### Claim 1

A semiconductor structure including III-N materials, comprising:
a support substrate;
a main layer made of III-N material, the main layer having a first section disposed on the support substrate and a second section disposed over the first section;
an interlayer made of III-N material disposed between the first section and the second section for compressing the second section of the main layer, wherein the interlayer comprises:
a lower layer disposed on the first section of the main layer; and
an upper layer disposed on and in contact with the lower layer formed by a superlattice, wherein the lower layer consists essentially of a homogeneous layer or a superlattice which is different from the superlattice constituting the upper layer, having a dislocation density greater than that of the upper layer and a lattice parameter smaller than a lattice parameter of the material forming the upper layer, the superlattice constituting the upper layer and, where appropriate, the superlattice constituting the lower layer being formed by a repetition of a pattern comprising at least two layers of different types; and wherein each layer making up the pattern has a thickness of between 0.5 nm and 50 nm, the interlayer has a thickness of between 200 nm and 1000 nm, and the upper layer comprises a p-type dopant of carbon, iron or magnesium in a concentration of between 5×1018 and 5x1019 at/cm3 to make the layer resistive.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the lattice parameter of the material forming the upper layer is smaller than the lattice parameter of the material forming the second section of the main layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the main layer and the interlayer are monocrystalline.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising a second interlayer on the second section of the main layer and a third section of the main layer disposed on the second interlayer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the second interlayer is formed by a uniform layer, a superlattice, or a combination thereof.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the support substrate has a lower coefficient of thermal expansion than the main layer.

### Claim 7 (depends on 1)

A semiconductor wafer comprising the semiconductor structure of claim 1.

### Claim 8 (depends on 1)

An integrated circuit device comprising the semiconductor structure of claim 1.