US 11,031,377 B2 · Integration of three-dimensional NAND memory devices with multiple functional chips

Abstract

Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.

Claims20

Dependent claims

A method for forming a three-dimensional semiconductor device, comprising:

forming a microprocessor chip, comprising:
forming at least one microprocessor device on a first substrate;
and
forming a first interconnect layer on the at least one microprocessor device, the first interconnect layer comprising at least one first interconnect structure;
forming a memory chip, comprising:
forming at least one memory cell on a second substrate;
and
forming a second interconnect layer on the at least one memory cell, the second interconnect layer comprising at least one second interconnect structure;
and
bonding the first interconnect layer of the microprocessor chip with the second interconnect layer of the memory chip, such that the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one memory cell of the memory chip through the at least one first interconnect structure or the at least one second interconnect structure.

7 more elements

A method for forming a three-dimensional semiconductor device, comprising:

forming a first memory chip, comprising:
forming at least one first memory cell on a first substrate;
and
forming a first interconnect layer on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure;
forming a second memory chip, comprising:
forming at least one second memory cell on a second substrate;
and
forming a second interconnect layer on the at least one second memory cell, the second interconnect layer comprising at least one second interconnect structure;
bonding the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, such that the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure or the at least one second interconnect structure;
forming a microprocessor chip, comprising:
forming at least one microprocessor device on a third substrate;
and
forming a third interconnect layer on the at least one microprocessor device, the third interconnect layer comprising at least one third interconnect structure;
and
bonding the third interconnect layer of the microprocessor chip with the first substrate of the first memory chip, such that the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one first memory cell of the first memory chip through the at least one first interconnect structure or the at least one third interconnect structure.

12 more elements

A three-dimensional semiconductor device, comprising:

a microprocessor chip, comprising:
at least one microprocessor device on a first substrate;
and
a first interconnect layer disposed on the at least one microprocessor device, the first interconnect layer comprising at least one first interconnect structure;
a first memory chip, comprising:
at least one first memory cell on a second substrate;
and
a second interconnect layer disposed on the at least one first memory cell, the second interconnect layer comprising at least one second interconnect structure;
and
a second memory chip, comprising:
at least one second memory cell on a third substrate;
and
a third interconnect layer disposed on the at least one second memory cell, the third interconnect layer comprising at least one third interconnect structure,
wherein the first interconnect layer of the microprocessor chip is bonded with the second substrate of the first memory chip, and the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one first memory cell of the first memory chip through the at least one first interconnect structure or the at least one second interconnect structure;
and
wherein the third interconnect layer of the second memory chip is bonded with the second interconnect layer of the first memory chip, and the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure, the at least second interconnect structure, or the at least one third interconnect structure.

13 more elements

Dependencies are inferred from the claim text.

Integration of three-dimensional NAND memory devices with multiple functional chips

Life of this patent

Integration of three-dimensional NAND memory devices with multiple functional chips

Life of this patent

Abstract

Claims20