US 11,031,090 B1 · Analog current memory with droop compensation

Abstract

An analog current memory circuit includes a ramp current generator producing a ramp current; a storage transistor, a write-enable transistor, a charge pump transistor, a clock generator producing a clock signal having a first state and a second state, a comparator electrically coupled to the storage transistor and the ramp current generator, a controller electrically coupled to the comparator and the clock generator, and a switch electrically coupled to the controller and the ramp current generator. During the write phase, the controller produces a write-enable signal to turn on the write-enable transistor to produce a stored current in the storage transistor, the stored current being substantially equal to an input current to the analog current memory circuit. During the compensation phase, the switch electrically couples the ramp current generator and the storage transistor to the comparator.

Claims14

Dependent claims

An analog current memory circuit operable in a write phase and a compensation phase, the compensation phase repeating a plurality of times after each write phase, comprising:

a ramp current generator producing a ramp current;
a storage transistor, a write-enable transistor, and a charge pump transistor;
a clock generator producing a clock signal having a first state and a second state;
a comparator electrically coupled to the storage transistor and the ramp current generator;
a controller electrically coupled to the comparator and the clock generator;
and
a switch electrically coupled to the controller and the ramp current generator;
wherein during the write phase, the controller produces a write-enable signal to turn on the write-enable transistor to produce a stored current in the storage transistor, the stored current being substantially equal to an input current to the analog current memory circuit;
and
during the compensation phase, the switch electrically couples the ramp current generator and the storage transistor to the comparator.

7 more elements

An analog current memory circuit organized in a plurality of rows and columns, each column comprising:

a plurality of current memory cells each memory cell operable in a write phase and a compensation phase, and each memory cell comprising a storage transistor, a write-enable transistor, a row select transistor, and a charge pump transistor;
a column line electrically coupled to said plurality of current memory cells;
a ramp current generator producing a current ramp;
a comparator electrically coupled to the column line and a bias voltage;
a clock signal having a first state and a second state;
a column switch electrically coupled to a column input current and the ramp current generator;
and
a column controller electrically coupled to the plurality of memory cells and the comparator.

5 more elements

Dependencies are inferred from the claim text.

Analog current memory with droop compensation

Life of this patent

Analog current memory with droop compensation

Life of this patent

Abstract

Claims14