Apparatuses and methods for decoding addresses for memory

An apparatus, comprising:

• a memory cell array including a bank of memory, the bank of memory including a plurality of groups of memory, each of the groups of memory including a plurality of sections of memory, each of the sections of memory including memory cells arranged in rows and columns of memory for the respective group;
• and
• a row decoder coupled to the bank of memory and configured to decode addresses and selectively activate a selected row of memory cells during a memory access operation, the row decoder further configured to decode the addresses to access a first group of memory of the plurality of groups of memory to include rows of prime memory from a first block of memory and to further include rows of prime memory from a second block of memory, and to further decode the addresses to access a second group of memory of the plurality of groups of memory to include rows of prime memory from the second block of memory and to further include rows of redundant memory, wherein the rows of redundant memory are shared with the first and second blocks of memory, wherein the first group of memory for the plurality of groups of memory includes all of the rows of prime memory for the first block of memory and the second group of memory of the plurality of groups of memory includes less than all of the rows for the second block of memory.

An apparatus, comprising:

• a memory cell array including a plurality of banks of memory and a plurality of sets of sense amplifiers, each of the banks of memory including memory cells arranged in rows and columns of memory, the rows and columns of memory included in a plurality of sections of memory, each set of sense amplifiers of the plurality of sets of sense amplifiers coupled to the columns of memory included in a section of memory of the plurality of sections of memory and each set of sense amplifiers of the plurality of sets of sense amplifiers configured to be activated when accessing a row of memory included in the section of memory that includes the columns of memory to which the set of sense amplifiers are coupled;
• and
• a plurality of row decoders, each configured to decode addresses and selectively activate a selected row of memory cells for access for a respective bank of memory, each row decoder of the plurality of row decoders further configured to access the rows of memory cells as blocks of memory, wherein each of the blocks of memory including rows of memory cells of a portion of at least one section of memory and wherein two different blocks of memory include rows of memory from a same section of memory.