# US 11,030,147 B2 · Hardware acceleration using a self-programmable coprocessor architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,147 B2 - Document ID: US11030147B2 - Status: Granted - Kind: B2 - Application number: 16/366,607 - Filed: 2019-03-27 - Published: 2020-10-01 - Granted: 2021-06-08 - Earliest claimed: 2019-03-27 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Justin Ginn; Tony E. Sawan - Web page: https://patentgrep.com/patent/US11030147B2 ## CPC - G06F 12/0862: with prefetch - G06F 15/82: data or demand driven - G06F 9/30101: {Special purpose registers} - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 15/7889: {Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877)} - G06F 2212/452: Instruction code - G06F 2212/6026: Prefetching based on access pattern detection, e.g. stride based prefetch - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction. ## Claims ### Claim 1 A method for hardware acceleration using a self-programmable coprocessor architecture, the method comprising: determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence; responsive to determining that the instruction cache comprises an accelerable instruction sequence: instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction; responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence: determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image; and synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence. ### Claim 2 (depends on 1) The method of claim 1, wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a value stored in a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache. ### Claim 3 (depends on 1) The method of claim 1, further comprising: determining that the instruction cache comprises the potentially accelerable instruction sequence; determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction. ### Claim 4 (depends on 3) The method of claim 3, wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex. ### Claim 5 (depends on 4) The method of claim 4, further comprising determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup. ### Claim 6 (depends on 1) The method of claim 1, further comprising verifying the synthesized accelerator image including comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image. ### Claim 7 (depends on 6) The method of claim 6, further comprising storing the synthesized accelerator image in a Complex Instruction Library comprising one or more entries each associating one of a plurality of complex instructions with a corresponding accelerator image. ### Claim 8 An apparatus for hardware acceleration using a self-programmable coprocessor architecture configured to carry out the steps of: determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence; responsive to determining that the instruction cache comprises an accelerable instruction sequence: instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction; responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence: determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image; and synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a signature generated by a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the steps further comprise: determining that the instruction cache comprises the potentially accelerable instruction sequence; determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the steps further comprise determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup. ### Claim 13 (depends on 8) The apparatus of claim 8, further comprising verifying the synthesized accelerator image including comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the steps further comprise storing the synthesized accelerator image in a Complex Instruction Library comprising one or more entries each associating one of a plurality of complex instructions with a corresponding accelerator image. ### Claim 15 A computer program product for hardware acceleration using a self-programmable coprocessor architecture, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of: determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence; responsive to determining that the instruction cache comprises an accelerable instruction sequence: instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction; responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence: determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image; synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence; and verifying the synthesized accelerator image. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a value stored in a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache. ### Claim 17 (depends on 16) The computer program product of claim 16, wherein the steps further comprise: determining that the instruction cache comprises the potentially accelerable instruction sequence; determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex. ### Claim 19 (depends on 18) The computer program product of claim 18, wherein the steps further comprise determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup. ### Claim 20 (depends on 15) The computer program product of claim 15, wherein verifying the synthesized accelerator image includes comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image.