# US 11,030,141 B2 · Apparatuses for independent tuning of on-die termination impedances and output driver impedances, and related methods, semiconductor devices, and systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,141 B2 - Document ID: US11030141B2 - Status: Granted - Kind: B2 - Application number: 16/737,182 - Filed: 2020-01-08 - Published: 2020-05-21 - Granted: 2021-06-08 - Earliest claimed: 2018-11-20 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Elancheren Durai - Web page: https://patentgrep.com/patent/US11030141B2 ## CPC - G06F 13/4086: {Bus impedance matching, e.g. termination} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/1066: {Output synchronization} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 11/40: using transistors - G11C 7/1045: {Read-write mode select circuits} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 2207/2254: Calibration - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus may include at least one output circuit configured to generate a desired output driver impedance (ODI) during a first operational mode. The least one output circuit may further be configured to independently generate a desired on-die termination (ODT) impedance during a second operational mode. Memory systems, memory devices, electronic systems, and related methods of operation are also described. ## Claims ### Claim 1 An apparatus, comprising: at least one circuit configured to: receive at least one signal indicative of an operational mode of the apparatus; generate, via activating at least one tuning device, a desired output driver impedance (ODI) value in response to the operational mode being a first operational mode; and generate, via activating at least one other tuning device, a desired on-die termination (ODT) impedance value in response to the operational mode being a second operational mode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the at least one circuit is further configured to generate another desired ODT impedance value during a write operation. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising a control device coupled to the at least one circuit and configured to determine whether the apparatus in operating in the first operational mode or the second operational mode. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the control device is configured to convey the at least one signal to the at least one circuit to generate one of the desired ODI value and the desired ODT impedance value. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the at least one circuit is configured to generate the desired ODI value based on a first parameter and generate the desired ODT impedance value based on a second, different parameter. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the at least one circuit comprises a calibration circuit configured to generate at least one of the desired ODI value and the desired ODT impedance value. ### Claim 7 A semiconductor device, comprising: at least one circuit including a number of tuning devices and configured to: tune, via at least one tuning device of the number of tuning devices of the at least one circuit, at least one impedance value of the semiconductor device responsive to the semiconductor device being in a first mode during a first read operation; and tune, via at least one other tuning device of the number of tuning devices, the at least one impedance value of the semiconductor device responsive to the semiconductor device being in a second mode during a second, different read operation. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the at least one impedance value comprises an output driver impedance (ODI) value, wherein the at least one circuit comprises a driver circuit configured to tune the ODI value based on a parameter responsive to the semiconductor device being in the first mode. ### Claim 9 (depends on 7) The semiconductor device of claim 7, wherein the at least one impedance value comprises an on-die termination (ODT) impedance value, wherein the at least one circuit comprises a driver circuit configured to tune the ODT impedance value based on a parameter responsive to the semiconductor device being in the second mode. ### Claim 10 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit comprises a driver circuit configured to tune the at least one impedance value based on one of a first parameter and a second, different parameter during a write operation. ### Claim 11 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit includes an output driver circuit including the number of tuning devices for tuning the at least one impedance value of the semiconductor device. ### Claim 12 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit includes a calibration circuit configured to determine at least one of a desired output driver impedance (ODI) and a desired on-die termination (ODT) impedance for the semiconductor device. ### Claim 13 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit is configured to determine whether the semiconductor device is in the first mode or the second mode based on a signal received from a controller coupled to the semiconductor device. ### Claim 14 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit is configured to determine whether the semiconductor device is in the first mode or the second mode based on at least one associated mode register setting. ### Claim 15 (depends on 7) The semiconductor device of claim 7, wherein the at least one circuit is configured to tune the at least one impedance value via one or more of the number of tuning devices. ### Claim 16 A system, comprising: at least one input device; at least one output device; at least one processor device operably coupled to the input device and the output device; and at least one memory system operably coupled to the at least one processor device, the memory system comprising: a first memory device configured to generate a first impedance based on a first parameter in response to the first memory device operating in a drive mode; and at least one second memory device configured to generate a second impedance based on a second, different parameter in response to the at least one second memory device operating in a termination mode. ### Claim 17 A method, comprising: determining an operational mode of each of a first device and at least one second device; tuning, via at least one tuning device, an output driver impedance (ODI) value of the first device in response to the first device operating in a first operational mode; and tuning, via at least one other tuning device, an on-die termination (ODT) value of the at least one second device in response to the at least one second device operating in a second operational mode. ### Claim 18 (depends on 17) The method of claim 17, wherein tuning the ODI value of the first device operating in the first operational mode comprises tuning the ODI value of the first device operating in the first operational mode based on a first parameter, and wherein independently tuning the ODT value of the at least one second device operating in the second operational mode comprises tuning the ODT value of the at least one second device operating in the second operational mode based on a second, different parameter. ### Claim 19 (depends on 17) The method of claim 17, wherein determining the operational mode comprises determining the operational mode of at least one of the first device and the at least one second device based on one or more signals received from a controller, one or more mode register settings, or a combination thereof.