# US 11,030,138 B2 · Circuit device, electronic device, and cable harness > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,138 B2 - Document ID: US11030138B2 - Status: Granted - Kind: B2 - Application number: 16/804,449 - Filed: 2020-02-28 - Published: 2020-06-25 - Granted: 2021-06-08 - Earliest claimed: 2018-03-27 - Assignees: Seiko Epson Corporation - Applicants: Seiko Epson Corporation - Inventors: Ryuichi Kagaya - Web page: https://patentgrep.com/patent/US11030138B2 ## CPC - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 2213/0042: Universal serial bus [USB] - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus, which are compliant with the USB standard, ON in a first period and OFF in a second period, and a processing circuit that performs processing for transferring a packet in a transfer route constituted by the first bus, the first and second physical layer circuits, and the second bus, in the second period. The second physical layer circuit includes a disconnection detection circuit that detects device disconnection of a device connected to the second bus side. If device disconnection is detected in the second period, the connection between the first bus and the second bus is switched from off to on after a wait period has elapsed from the timing at which the device disconnection was detected. ## Claims ### Claim 1 A circuit device comprising: a first bus compliant with a USB standard for connection; a second bus compliant with the USB standard for connection; a bus switch circuit that, having one end configured to be connected to the first bus and another end configured to be connected to the second bus, switches on connection between the first bus and the second bus in a first period, and switches off the connection in a second period; a processing circuit that performs, in the second period, transfer processing for transmitting a packet received from the first bus to the second bus, and transmitting a packet received from the second bus to the first bus; and a second-bus-side disconnection detection circuit that detects device disconnection of a device connected to the second bus side, wherein when device connection of a device connected to the second bus is detected by the second-bus-side disconnection detection circuit, the bus switch circuit, in the second period, switches the connection between the first bus and the second bus from off to on after a wait period has elapsed from a timing at which the device disconnection of device connected to the second bus is detected. ### Claim 2 (depends on 1) The circuit device according to claim 1, further comprising a timer circuit that measures an elapse of the wait period from the timing at which the device disconnection is detected. ### Claim 3 (depends on 1) The circuit device according to claim 1, wherein TW>TSF is satisfied, where TSF is an issue interval of a Start of Frame (SOF) packet and TW is a length of the wait period. ### Claim 4 (depends on 3) The circuit device according to claim 3, wherein TW≥2×TSF is satisfied. ### Claim 5 (depends on 1) The circuit device according to claim 1, wherein, when the device disconnection of a device connected to the second bus is detected by the second-bus-side disconnection detection circuit and the bus switch circuit switches connection between the first bus and the second bus from off to on after the wait period has elapsed from the timing at which the device disconnection is detected, the processing circuit stops the transfer processing. ### Claim 6 (depends on 1) The circuit device according to claim 1, further comprising: a first-bus-side disconnection detection circuit that detects device disconnection of a device connected to the first bus, wherein when connection between the first bus and the second bus is off, and when device disconnection of a device connected to the first bus is detected by the first-bus-side disconnection detection circuit, the bus switch circuit switches the connection between the first bus and the second bus from off to on after a wait period has elapsed from a timing at which the device disconnection of a device connected to the first bus is detected. ### Claim 7 (depends on 6) The circuit device according to claim 6, further comprising: a first upstream port detection circuit that detects whether or not the first bus is a bus on an upstream side; and a second upstream port detection circuit that detects whether or not the second bus is a bus on the upstream side, wherein when the first bus is determined to be a bus on the upstream side, the second-bus-side disconnection detection circuit detects device disconnection of a device connected to the second bus, and when the second bus is determined to be a bus on the upstream side, the first-bus-side disconnection detection circuit detects device disconnection of a device connected to the first bus. ### Claim 8 (depends on 7) The circuit device according to claim 7, wherein the first upstream port detection circuit determines, when a packet received from the first bus is detected to be a Start of Frame (SOF) packet, that the first bus is a bus on the upstream side, and the second upstream port detection circuit determines, when a packet received from the second bus is detected to be an SOF packet, that the second bus is a bus on the upstream side. ### Claim 9 (depends on 1) The circuit device according to claim 1, wherein the processing circuit, upon receiving a Start of Frame (SOF) packet from the first bus, performs processing for transmitting a repeat packet of the SOF packet to the second bus, and the second-bus-side disconnection detection circuit detects device disconnection of a device connected to the second bus by detecting a signal amplitude of an End of Packet (EOP) in the repeat packet of the SOF packet. ### Claim 10 (depends on 1) The circuit device according to claim 1, further comprising a bus monitor circuit that performs operation of monitoring the first bus and the second bus, wherein the bus switch circuit switches connection between the first bus and the second bus on or off based on a monitoring result of the bus monitor circuit. ### Claim 11 (depends on 10) The circuit device according to claim 10, wherein, when device disconnection of a device connected of the second bus is detected by the second-bus-side disconnection detection circuits, the bus monitor circuit outputs a signal for stopping the transfer processing of the processing circuit to the processing circuit, and outputs a signal for switching connection between the first bus and the second bus from off to on to the bus switch circuit, after the wait period has elapsed from the timing at which device disconnection of a device connected of the second bus is detected. ### Claim 12 (depends on 1) An electronic device comprising: the circuit device according to claim 1; and a processing device to be connected to the first bus. ### Claim 13 (depends on 1) A cable harness comprising: the circuit device according to claim 1; and a cable.