# US 11,030,135 B2 · Method and apparatus for power reduction for data movement

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- Number: US 11,030,135 B2
- Document ID: US11030135B2
- Status: Granted
- Kind: B2
- Application number: 16/212,930
- Filed: 2018-12-07
- Published: 2019-04-11
- Granted: 2021-06-08
- Earliest claimed: 2012-12-20
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Greg Sadowski
- Web page: https://patentgrep.com/patent/US11030135B2

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.

## Claims

### Claim 1

A method of receiving data including:
receiving, by a controller, a first data entry and a second data entry of a set of data entries from a first buffer in a first order such that the second data entry is received before the first data entry at least partially due to the similarity between the first and second entries, wherein the first entry was written to the first buffer before the second entry was written to the first buffer,
receiving, by the controller, at least one index along with the first data entry and the second data entry, and
writing, by the controller, the first data entry to a first slot in a second buffer in a second order and the second data entry to a second slot in the second buffer in the second order, the first slot and the second slot being identified by the at least one index.

### Claim 2 (depends on 1)

The method of claim 1, the at least one index comprising a first index and a second index such that the first index identifies the first slot and the second index identifies the second slot.

### Claim 3 (depends on 2)

The method of claim 2, further including:
outputting, by an output, the first data entry from the second buffer in the second order relative to the second data entry, the second order being described by at least one of the first and second indexes.

### Claim 4 (depends on 2)

The method of claim 2, wherein the second order is described by both the first and second indexes.

### Claim 5

A data storage including:
a plurality of data storage slots;
a controller operable to:
receive, from a buffer, a first data entry and a second data entry of a set of data entries in a first order such that the second data entry is received before the first data entry at least partially due to the similarity between the first and second entries, wherein the first entry was written to the buffer before the second entry was written to the buffer;
receive an index; and
place the first data entry into a first slot of the plurality of data storage slots and the second data entry into a second slot of the plurality of data storage slots, the first slot and the second slot being identified at least partially based on the index; and
an output, operable to output data entries, including the first data entry and the second data entry, in a second order proscribed by the index.

### Claim 6 (depends on 5)

The data storage of claim 5, wherein the data storage is DRAM.

### Claim 7 (depends on 5)

The data storage of claim 5, wherein the controller includes state logic operable to receive the index and place the first data entry and the second data entry according to the index.

### Claim 8

A system comprising:
a transmission processor comprising a transmission controller operable to determine a first order of transfer for a set of data entries to be transferred that reduces an amount of power needed to complete the transfer, wherein the transmission controller is operable to:
determine a first difference between a previously transferred data entry and the first data entry of the data entries to be transferred,
determine a second difference between each of the data entries to be transferred and other data entries of the data entries to be transferred, and
determine the first order of transfer based on the determined first and second differences such that the data entries to be transferred have the smallest difference relative to the previously transferred data entry; and
a reception data storage comprising a reception controller and a buffer operable to store the data entries, wherein the reception controller is operable to:
receive a first data entry and a second data entry of the data entries in the first order,
receive at least one index along with the first data entry and the second data entry, and
write the first data entry to a first slot in the buffer in a second order and the second data entry to a second slot in the buffer in the second order; the first slot and the second slot being identified by the at least one index.

### Claim 9 (depends on 8)

The system of claim 8, the at least one index comprising a first index and a second index such that the first index identifies the first slot and the second index identifies the second slot.

### Claim 10 (depends on 9)

The system of claim 9, wherein the reception data storage further comprises an output operable to output the first data entry from the buffer in the second order relative to the second data entry, the relative second order being described by at least one of the first and second indexes.

### Claim 11 (depends on 9)

The system of claim 9, wherein the second order is described by both the first and second indexes.

### Claim 12 (depends on 8)

The system of claim 8, wherein the transmission processor further comprises a transmitter operable to transmit the data entries in the first order.

### Claim 13 (depends on 8)

The system of claim 8, wherein the transmission controller is further operable to determine if a second data entry has an age above a first threshold age.

### Claim 14 (depends on 13)

The system of claim 13, wherein the transmission controller is further operable to determine the first order of transmission that will require a lowest amount of power to complete from those orders that successfully achieve transmission of the second data entry prior to the second data entry reaching a second threshold age.

### Claim 15 (depends on 8)

The system of claim 8, wherein the first order requires a lowest amount of power to complete relative to other possible orders of transmission.