# US 11,030,130 B2 · Storage device, access method and system utilizing the same

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- Number: US 11,030,130 B2
- Document ID: US11030130B2
- Status: Granted
- Kind: B2
- Application number: 16/840,818
- Filed: 2020-04-06
- Published: 2021-02-18
- Granted: 2021-06-08
- Earliest claimed: 2019-08-15
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Chih-Wei Liang
- Web page: https://patentgrep.com/patent/US11030130B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 2207/2236: Copy
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.

## Claims

### Claim 1

A storage device comprising:
a memory array comprising:
a plurality of banks; and
a data path; and
a peripheral logic circuit operating in a copy mode or a normal mode according to a mode-switch command,
wherein in the copy mode:
the peripheral logic circuit decodes an activation command to generate activation information and activates a portion of the banks according to the activation information,
the peripheral logic circuit decodes a copy command to generate source information and assigns one among the portion of the banks as a source bank according to the source information,
the peripheral logic circuit performs a specific operation for the activation information and the source information to generate write information and assigns another one of the portion of the banks as a first target bank according to the write information, and
the peripheral logic circuit directs the source bank to output specific data to the data path and directs the target bank to receive and store the specific data from the data path.

### Claim 2 (depends on 1)

The storage device as claimed in claim 1,
wherein in the normal mode:
the peripheral logic circuit provides external data to the data path according to a write command and directs the first target bank to store the external data; and
the peripheral logic circuit directs the source bank to provide the specific data to the data path according to a read command and outputs the specific data from the data path to an external interface.

### Claim 3 (depends on 1)

The storage device as claimed in claim 1, wherein the specific operation is a XOR operation.

### Claim 4 (depends on 1)

The storage device as claimed in claim 1, wherein the peripheral logic circuit further assigns another one of the portion of the banks as a second target bank according to the write information, and directs the second target bank to receive and store the specific data from the data path.

### Claim 5 (depends on 1)

The storage device as claimed in claim 1, wherein the memory array comprises:
a first access circuit enabling a plurality of bit lines of the source bank according to a column enable signal and amplifying data stored in a plurality of first cells coupled to the bit lines to generate amplified data;
a second access circuit amplifying the amplified data to generate the specific data according to a first control signal; and
a third access circuit writing the specific data into a plurality of second cells of the first target bank according to a second control signal.

### Claim 6 (depends on 4)

The storage device as claimed in claim 4, wherein the peripheral logic circuit comprises:
a command decoder circuit decoding the copy command to generate the column enable signal;
a first delay circuit delaying the column enable signal to generate the first control signal; and
a second delay circuit delaying the first control signal to generate the second control signal.

### Claim 7 (depends on 4)

The storage device as claimed in claim 4, wherein the peripheral logic circuit comprises:
a command decoder circuit decoding the copy command to generate the column enable signal; and
a counter having a first count value and a second count value, wherein in response to the first count value reaching a first predetermined value, the counter generates the first control signal, and in response to the second count value reaching a second predetermined value, the counter generates the second control signal.

### Claim 8

An access method for a storage device comprising a plurality of banks, comprising:
receiving a mode-switch command to operate in a copy mode or a normal mode;
in the copy mode:
decoding an activation command to generate activation information;
activating a portion of the plurality of banks according to the activation information;
decoding a copy command to generate source information;
assigning one of the portion of the plurality of banks as a source bank according to the source information;
performing a specific operation for the activation information and the source information to generate write information;
assigning another one of the portion of the plurality of banks as a first target bank according to the write information;
directing the source bank to provide specific data to a data path; and
directing the first target bank to store the specific data from the data path;
in the normal mode:
providing external data to the data path according to a write command and directing the first target bank to store the external data; and
directing the source bank to provide the specific data to the data path and outputting the specific data from the data path to an external interface.

### Claim 9 (depends on 8)

The access method as claimed in claim 8, wherein the specific operation is an XOR operation.

### Claim 10 (depends on 8)

The access method as claimed in claim 8, further comprising:
assigning another one of the portion of the plurality of banks as a second target banks according to the write information; and
directing the second target bank to store the specific data from the data path according to the write information.

### Claim 11 (depends on 10)

The access method as claimed in claim 10, further comprising:
decoding the copy command to enable a plurality of bit lines of the source bank;
amplifying data stored in a plurality of first cells coupled to the bit lines to generate amplified data;
amplifying the amplified data to generate the specific data; and
directing the first and second target banks to simultaneously store the specific data.

### Claim 12 (depends on 10)

The access method as claimed in claim 10, further comprising:
decoding the copy command to enable a plurality of bit lines of the source bank;
amplifying data stored in a plurality of first cells coupled to the bit lines to generate amplified data;
determining whether a first count value reaches a first predetermined value, wherein in response to the first count value reaching the first predetermined value, the amplified data is amplified to generate the specific data; and
determining whether a second count value reaches a second predetermined value, wherein in response to the second count value reaching the second predetermined value, the first and second target banks store the specific data from the data path.

### Claim 13

An access system comprising:
a controller configured to generate a mode-switch command, wherein after the controller sends the mode-switch command, the controller generates an activation command and a copy command; and
a storage device operating according to the mode-switch command, the activation command and the copy command and comprising:
a memory array comprising:
a plurality of banks; and
a data path coupled to the plurality of banks; and
a peripheral logic circuit operating in a copy mode or a normal mode according to the mode-switch command,
wherein in the copy mode:
the peripheral logic circuit decodes the activation command to generate activation information and activates a portion of the banks according to the activation information,
the peripheral logic circuit decodes the copy command to generate source information and assigns one among the portion of the banks as a source bank according to the source information,
the peripheral logic circuit performs a specific operation for the activation information and the source information to generate write information and assigns another one of the portion of the banks as a first target bank according to the write information, and
the peripheral logic circuit directs the source bank to output specific data to the data path and directs the target bank to receive and store the specific data from the data path.

### Claim 14 (depends on 13)

The access system as claimed in claim 13, wherein the memory array comprises:
a first access circuit enabling a plurality of bit lines of the source bank according to a column enable signal and amplifying data stored in a plurality of first cells coupled to the bit lines to generate amplified data;
a second access circuit coupled to the data path and amplifying the amplified data to generate the specific data to the data path according to a first control signal; and
a third access circuit coupled to the data path and transmitting the specific data from the data path to a plurality of second cells of the first target bank according to a second control signal.

### Claim 15 (depends on 14)

The access system as claimed in claim 14, wherein the peripheral logic circuit comprises:
a read circuit;
a write circuit; and
a determining circuit providing the copy command to the read circuit or the write circuit according to the copy command.

### Claim 16 (depends on 15)

The access system as claimed in claim 15, wherein in response to the copy command being a read command, the determining circuit provides the copy command to the read circuit,
wherein the read circuit comprises:
a command decoder circuit decoding the copy command to generate the column enable signal;
a first delay circuit delaying the column enable signal to generate the first control signal; and
a second delay circuit delaying the first control signal to generate the second control signal.

### Claim 17 (depends on 16)

The access system as claimed in claim 16, wherein in response to the copy command being a write command, the determining circuit provides the copy command to the write circuit,
wherein the write circuit comprises:
a command decoder circuit decoding the copy command to generate the column enable signal; and
a counter having a first count value and a second count value, wherein in response to the first count value reaching a first predetermined value, the counter generates the first control signal, and in response to the second count value reaching a second predetermined value, the counter generates the second control signal.

### Claim 18 (depends on 1)

The storage device as claimed in claim 1, wherein the peripheral logic circuit comprises:
a command decoder circuit decoding the copy command to generate a column enable signal;
a first delay circuit delaying the column enable signal to generate the first control signal;
a second delay circuit delaying the first control signal to generate the second control signal;
an amplifier circuit amplifying data stored in the source bank according to the first control signal to generate the specific data;
a write driver transmitting the specific data on the data path to the first target bank according to the second control signal.