# US 11,030,126 B2 · Techniques for managing access to hardware accelerator memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,126 B2 - Document ID: US11030126B2 - Status: Granted - Kind: B2 - Application number: 15/650,112 - Filed: 2017-07-14 - Published: 2019-01-17 - Granted: 2021-06-08 - Earliest claimed: 2017-07-14 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: David A. Koufaty; Rajesh M. Sankaran; Stephen R. Van Doren - Web page: https://patentgrep.com/patent/US11030126B2 ## CPC - G06F 13/1663: {Access to shared memory} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 9/467: {Transactional memory (G06F9/528 takes precedence)} - G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/10: Address translation - G06F 13/1668: {Details of memory controller} - G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory} - G06F 21/71: to assure secure computing or processing of information - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 12/0888: using selective caching, e.g. bypass - G06F 2212/1016: Performance improvement - G06F 2212/302: In image processor or graphics adapter - G06F 2212/502: using adaptive policy - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed. ## Claims ### Claim 1 An apparatus to provide coherence bias for accessing accelerator memory, the apparatus comprising: at least one processor; a logic device communicatively coupled to the at least one processor; a logic device memory communicatively coupled to the logic device, the logic device memory to store bias information; and logic, at least a portion comprised in hardware, the logic to: receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request based on the bias information stored in the logic device memory, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. ### Claim 2 (depends on 1) The apparatus of claim 1, the logic device comprising an accelerator and the logic device memory comprising an accelerator memory. ### Claim 3 (depends on 1) The apparatus of claim 1, the bias mode comprising one of a host bias mode and the device bias mode. ### Claim 4 (depends on 1) The apparatus of claim 1, the logic to provide the logic device with access to the logic device memory via a host bias pathway responsive to the bias mode being a host bias mode. ### Claim 5 (depends on 1) The apparatus of claim 1, the logic to: receive a request to access the logic device memory from the at least one processor, and provide data from the logic device memory to the at least one processor as an uncached request responsive to the bias mode being a device bias mode. ### Claim 6 (depends on 1) The apparatus of claim 1, the logic device communicatively coupled to the at least one processor via a multi-protocol link operative to support a plurality of communication protocols, the plurality of communication protocols comprising at least two of an intra-device protocol, a memory interconnect protocol, or a fabric-based protocol. ### Claim 7 (depends on 1) The apparatus of claim 1, the at least one processor comprising at least one coherency controller operative to provide at least one standard cache coherency protocol, the logic to provide the logic device with access to the logic device memory via a host bias pathway responsive to the bias mode being a host bias mode, the host bias pathway flowing at least partially through the at least one coherency controller. ### Claim 8 (depends on 1) The apparatus of claim 1, the logic to determine the bias mode via a bias table comprising a bias indicator for a plurality of regions of the logic device memory. ### Claim 9 (depends on 1) The apparatus of claim 1, the logic to receive a request to transition the bias mode from a first bias mode to a second bias mode. ### Claim 10 (depends on 1) The apparatus of claim 1, the logic to perform a cache flushing operation responsive to a transition of the bias mode from a host bias mode to a device bias mode. ### Claim 11 A method to provide coherence bias for accessing accelerator memory, the method comprising: receiving a request to access a logic device memory from a logic device communicatively coupled to the logic device memory, the logic device communicatively coupled to at least one processor; determining a bias mode associated with the request based on bias information stored in the logic device memory; and providing the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. ### Claim 12 (depends on 11) The method of claim 11, the logic device comprising an accelerator and the logic device memory comprising an accelerator memory. ### Claim 13 (depends on 11) The method of claim 11, the bias mode comprising one of a host bias mode and the device bias mode. ### Claim 14 (depends on 11) The method of claim 11, comprising providing the logic device with access to the logic device memory via a host bias pathway responsive to the bias mode being a host bias mode. ### Claim 15 (depends on 11) The method of claim 11, comprising: receiving a request to access the logic device memory from the at least one processor, and providing data from the logic device memory to the at least one processor as an uncached request responsive to the bias mode being a device bias mode. ### Claim 16 (depends on 11) The method of claim 11, the logic device communicatively coupled to the at least one processor via a multi-protocol link operative to support a plurality of communication protocols, the plurality of communication protocols comprising at least two of an intra-device protocol, a memory interconnect protocol, or a fabric-based protocol. ### Claim 17 (depends on 11) The method of claim 11, comprising providing the logic device with access to the logic device memory via a host bias pathway responsive to the bias mode being a host bias mode, the host bias pathway flowing at least partially through at least one coherency controller of the at least one processor, the at least one coherency controller operative to provide at least one standard cache coherency protocol. ### Claim 18 (depends on 11) The method of claim 11, comprising determining the bias mode via a bias table comprising a bias indicator for a plurality of regions of the logic device memory. ### Claim 19 (depends on 11) The method of claim 11, comprising receiving a request to transition the bias mode from a first bias mode to a second bias mode. ### Claim 20 (depends on 11) The method of claim 11, comprising performing a cache flushing operation responsive to a transition of the bias mode from a host bias mode to a device bias mode. ### Claim 21 A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a computing device to provide coherence bias for accessing accelerator memory, the instructions to cause the computing device to: receive a request to access a logic device memory from a logic device communicatively coupled to the logic device memory, the logic device communicatively coupled to at least one processor; determine a bias mode associated with the request based on bias information stored in the logic device memory; and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. ### Claim 22 (depends on 21) The computer-readable storage medium of claim 21, the logic device comprising an accelerator and the logic device memory comprising an accelerator memory. ### Claim 23 (depends on 21) The computer-readable storage medium of claim 21, the bias mode comprising one of a host bias mode and the device bias mode. ### Claim 24 (depends on 21) The computer-readable storage medium of claim 21, the instructions to cause the computing device to: receive a request to access the logic device memory from the at least one processor, and provide data from the logic device memory to the at least one processor as an uncached request responsive to the bias mode being a device bias mode. ### Claim 25 (depends on 21) The computer-readable storage medium of claim 21, the instructions to cause the computing device to provide the logic device with access to the logic device memory via a host bias pathway responsive to the bias mode being a host bias mode, the host bias pathway flowing at least partially through at least one coherency controller of the at least one processor, the at least one coherency controller operative to provide at least one standard cache coherency protocol.