# US 11,030,124 B2 · Semiconductor device with secure access key and associated methods and systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,124 B2 - Document ID: US11030124B2 - Status: Granted - Kind: B2 - Application number: 16/677,376 - Filed: 2019-11-07 - Published: 2021-05-13 - Granted: 2021-06-08 - Earliest claimed: 2019-11-07 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Brenton P. Van Leeuwen; Nathaniel J. Meier - Web page: https://patentgrep.com/patent/US11030124B2 ## CPC - G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings} - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 12/1441: {for a range} - G06F 12/1466: {Key-lock mechanism} - G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) - G06F 2212/1052: Security improvement - G06F 2212/7206: Reconfiguration of flash memory system - G11C 11/1695: {Protection circuits or methods} - G11C 13/0059: {Security or protection circuits or methods} - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - H04L 9/08: Key distribution {or management, e.g. generation, sharing or updating, of cryptographic keys or passwords (network architectures or network communication protocols for supporting key management in a packet data network H04L63/06)} - H04L 2463/062: applying encryption of the keys - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison. ## Claims ### Claim 1 A memory device, comprising: a memory array; a plurality of nonvolatile memory elements configured to store a first access key; and peripheral circuitry coupled to the plurality of nonvolatile memory elements and the memory array, and configured to: receive a predetermined sequence of signals from a host device; retrieve the first access key from the plurality of nonvolatile memory elements in response to receiving the predetermined sequence of signals; configure one or more pins to output the first access key; and transmit the first access key using the one or more pins after configuring the one or more pins. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the one or more pins are designated for otherwise receiving inputs only. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the plurality of nonvolatile memory elements includes one or more fuses of a fuse array of the memory device, one or more conductive layers of the memory device, or both. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the peripheral circuitry is configured to generate control signals for a fuse array of the memory device in response to receiving an access command directed to the fuse array, the access command including a second access key. ### Claim 5 (depends on 4) The memory device of claim 4, further comprising: an authentication component coupling the peripheral circuitry with the fuse array, the authentication component configured to: receive the first access key and the second access key from the peripheral circuitry; compare the first access key with the second access key to determine whether the second access key corresponds to the first access key; and determine whether to permit or prohibit execution of the access command at the fuse array based on comparing the first access key with the second access key. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the authentication component is configured to block the control signals from reaching the fuse array when the second access key is different from the first access key, the control signals comprising one or more addresses of fuses of the fuse array, a read command associated with the one or more addresses, a write command associated with the one or more addresses, or a combination thereof. ### Claim 7 (depends on 5) The memory device of claim 5, wherein the authentication component is configured to disable a voltage source coupled with the fuse array and configured to generate a fuse programming voltage. ### Claim 8 (depends on 5) The memory device of claim 5, wherein the authentication component is configured to disable the peripheral circuitry, wherein the peripheral circuitry is further configured to perform test mode functions different from generating the control signals for the fuse array. ### Claim 9 (depends on 5) The memory device of claim 5, wherein the authentication component is configured to nullify the access command when the second access key is different from the first access key. ### Claim 10 A method, comprising: receiving a predetermined sequence of signals from a host device through a first set of pins of a memory device; retrieving a first access key from a plurality of nonvolatile memory elements of the memory device in response to receiving the predetermined sequence of signals; configuring a second set of pins of the memory device to output the first access key; and transmitting the retrieved first access key to the host device using the second set of pins after configuring the second set of pins. ### Claim 11 (depends on 10) The method of claim 10, wherein the second set of pins are designated for otherwise receiving inputs only from the host device. ### Claim 12 (depends on 10) The method of claim 10, further comprising: receiving an access command from the host device, the access command directed to a fuse array of the memory device and including a second access key; and generating control signals for the fuse array in response to receiving the access command, the control signals including one or more addresses of fuses of the fuse array, a read command associated with the one or more addresses, a write command associated with the one or more addresses, or a combination thereof. ### Claim 13 (depends on 12) The method of claim 12, further comprising: comparing the first access key with the second access key to determine whether the second access key corresponds to the first access key; and determining whether to permit or prohibit execution of the access command at the fuse array based on comparing the first access key with the second access key. ### Claim 14 (depends on 13) The method of claim 13, wherein prohibiting the execution when the second access key is different from the first access key includes: blocking the control signals from reaching the fuse array; disabling a voltage source coupled with the fuse array and configured to generate a fuse programming voltage; or disabling circuitry of the memory device configured to perform test mode functions different from generating the control signals for the fuse array. ### Claim 15 A system, comprising: a host device configured to: transmit a predetermined sequence of signals through a first channel coupled with a memory device; and monitor a second channel coupled with the memory device for a first access key sent from the memory device in response to receiving the predetermined sequence of signals; wherein the memory device is configured to: receive the predetermined sequence of signals through the first channel; retrieve the first access key from a plurality of nonvolatile memory elements in response to receiving the predetermined sequence of signals; configure one or more pins of the memory device to output the first access key, wherein the one or more pins are coupled with the second channel; and transmit the first access key to the host device using the one or more pins. ### Claim 16 (depends on 15) The system of claim 15, wherein the one or more pins of the memory device are designated for otherwise only receiving signals from the host device. ### Claim 17 (depends on 15) The system of claim 15, wherein the predetermined sequence of signals corresponds to a predetermined sequence of two or more commands directed to the memory device. ### Claim 18 (depends on 15) The system of claim 15, wherein the predetermined sequence of signals corresponds to a predetermined combination of two or more voltage levels as a function of time during a fixed duration. ### Claim 19 (depends on 15) The system of claim 15, wherein the host device is further configured to: receive the first access key sent from the memory device through the second channel; and generate an access command directed to a fuse array of the memory device, the access command including the first access key. ### Claim 20 (depends on 15) The system of claim 15, wherein the memory device is further configured to: retrieve the first access key from the plurality of nonvolatile memory elements in response to receiving an access command from the host device directed to a fuse array of the memory device, wherein the access command includes a second access key; compare the first access key with the second access key to determine whether the second access key corresponds to the first access key; and determine whether to permit or prohibit execution of the access command at the fuse array based on comparing the first access key with the second access key.