# US 11,030,115 B2 · Dataless cache entry

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- Number: US 11,030,115 B2
- Document ID: US11030115B2
- Status: Granted
- Kind: B2
- Application number: 16/455,219
- Filed: 2019-06-27
- Published: 2020-12-31
- Granted: 2021-06-08
- Earliest claimed: 2019-06-27
- Assignees: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
- Applicants: LENOVO Enterprise Solutions (Singapore) PTE. LTD.
- Inventors: Daniel J Colglazier
- Web page: https://patentgrep.com/patent/US11030115B2

## CPC

- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1044: Space efficiency improvement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus for using a dataless cache entry includes a cache memory and a cache controller configured to identify a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm, compare a data value of the first cache entry to a predefined value, and write a memory address tag and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value, wherein the dataless cache entry in the cache memory stores a memory address tag and state bits associated with the memory address, wherein the dataless cache entry represents the predefined value, and wherein the dataless cache entry occupies fewer bits than the first cache entry.

## Claims

### Claim 1

A method comprising:
identifying a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm;
comparing a data value of the first cache entry to a predefined value; and
storing a memory address tag and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value, wherein the dataless cache entry in the cache memory stores a memory address tag and state bits associated with the memory address tag, wherein the dataless cache entry represents the predefined value, and wherein the dataless cache entry occupies fewer bits than the first cache entry.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
identifying a second cache entry as a potential cache entry to be replaced in response to the data value of the first cache entry not matching the predefined value;
comparing a data value of the second cache entry to the predefined value; and
storing a memory address tag and state bits of the second cache entry to a dataless cache entry in response to the data value of the second cache entry matching the predefined value, wherein the dataless cache entry in the cache memory stores a memory address tag and state bits associated with the memory address tag, wherein the dataless cache entry represents the predefined value, and wherein the dataless cache entry occupies fewer bits than the second cache entry.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
identifying a cache entry for eviction according to the cache replacement algorithm in response to not finding a cache entry in cache memory matching the predefined value; and
evicting the cache entry.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first cache entry that is a valid cache entry and the dataless cache entry represents the first cache entry as valid data.

### Claim 5 (depends on 1)

The method of claim 1, further comprising returning the predefined value in response to a cache read hit for the dataless cache entry.

### Claim 6 (depends on 1)

The method of claim 1, wherein the predefined value is zero.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cache memory comprises a plurality of cache replacement groups, wherein each cache replacement group comprises a plurality of cache entries and at least one dataless cache entry.

### Claim 8 (depends on 7)

The method of claim 7:
wherein identifying a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm comprises identifying a cache entry in a cache replacement group;
wherein comparing the data value of the first cache entry to the predefined value comprises comparing a data value of the cache entry in the cache replacement group; and
wherein storing a memory address tag and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value comprises storing a memory address tag and state bits of the cache entry of the cache replacement group to the dataless cache entry of the cache replacement group in response to the data value of the cache entry of the cache replacement group matching the predefined value.

### Claim 9 (depends on 1)

The method of claim 1, wherein the dataless cache entry stores zero, one or more indicator bits, wherein the indicator bits indicate the predefined value.

### Claim 10 (depends on 1)

The method of claim 1, wherein the dataless cache entry is associated with a second memory address prior to storing the memory address and state bits of the first cache entry, the method further comprising:
examining the state bits of the dataless cache entry associated with the second memory address; and
writing back the predefined value to the second memory address prior to storing the memory address and state bits of the first cache entry in response to the state bits of the dataless cache entry associated with the second memory address indicating modification of the value of the second memory address.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
detecting whether a cache write hit matches a memory address stored to the dataless cache entry; and
converting the cache write hit into a cache write miss in response to the cache write hit matching a memory address stored to the dataless cache entry.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
identifying a second cache entry for eviction in the cache memory according to the cache replacement algorithm; and
transferring the memory address and state bits of the dataless cache entry to the second cache entry and writing data of the cache write hit to the second cache entry.

### Claim 13 (depends on 12)

The method of claim 12, further comprising invalidating the dataless cache entry.

### Claim 14

An apparatus comprising:
a cache memory comprising a dataless cache entry, wherein the dataless cache entry stores a memory address tag and state bits associated with the memory address tag, wherein the dataless cache entry represents the predefined value; and
a cache controller that:
identifies a first cache entry in the cache memory as a potential cache entry to be replaced according to a cache replacement algorithm;
compares a data value of the first cache entry to a predefined value; and
writes a memory address tag and state bits of the first cache entry to the dataless cache entry in response to the data value of the first cache entry matching the predefined value, wherein the dataless cache entry occupies fewer bits than the first cache entry.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the first cache entry that is a valid cache entry and the dataless cache entry represents the first cache entry as valid data.

### Claim 16 (depends on 14)

The apparatus of claim 14, further comprising returning the predefined value in response to a cache read hit for the dataless cache entry.

### Claim 17 (depends on 14)

The apparatus of claim 14, wherein the cache memory comprises a plurality of cache replacement groups, wherein each cache replacement group comprises a plurality of cache entries and at least one dataless cache entry.

### Claim 18 (depends on 17)

The apparatus of claim 17:
wherein identifying a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm comprises identifying a cache entry in a cache replacement group;
wherein comparing the data value of the first cache entry to the predefined value comprises comparing a data value of the cache entry in the cache replacement group; and
wherein storing a memory address and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value comprises storing a memory address and state bits of the cache entry of the cache replacement group to the dataless cache entry of the cache replacement group in response to the data value of the cache entry of the cache replacement group matching the predefined value.

### Claim 19 (depends on 14)

The apparatus of claim 14, wherein the cache controller further:
detects whether a cache write hit matches a memory address tag stored to the dataless cache entry; and
converts the cache write hit into a cache write miss in response to the cache write hit matching a memory address tag stored to the dataless cache entry.

### Claim 20

A system comprising:
a central processing unit (“CPU”);
a main memory;
a CPU cache comprising a set of dynamic-value cache entries and a fixed-value entry, wherein the fixed-value cache entry in the CPU cache stores a memory address tag and state bits associated with the memory address tag, wherein the dataless cache entry represents the predefined value, and wherein the fixed-cache entry occupies fewer bits than a dynamic-value cache entry, wherein data from the main memory is fetched to the CPU cache; and
a cache controller that:
identifies a first dynamic-value cache entry as a potential cache entry to be replaced according to a cache replacement algorithm;
compares a data value of the first dynamic-value cache entry to a predefined value; and
writes a memory address tag and state bits of the first dynamic-value cache entry to the fixed-value cache entry in response to the data value of the first dynamic-value cache entry matching the predefined value.