# US 11,030,110 B2 · Integrated circuit and data processing system supporting address aliasing in an accelerator

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- Number: US 11,030,110 B2
- Document ID: US11030110B2
- Status: Granted
- Kind: B2
- Application number: 16/395,942
- Filed: 2019-04-26
- Published: 2019-10-31
- Granted: 2021-06-08
- Earliest claimed: 2018-04-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael S. Siegel; Bartholomew Blaner; Jeffrey A. Stuecheli; William J. Starke; Derek E. Williams; Kenneth M. Valk; John D. Irish; Lakshminarayana Arimilli
- Web page: https://patentgrep.com/patent/US11030110B2

## CPC

- G06F 12/10: Address translation
- G06F 3/061: {Improving I/O performance}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 12/0817: using directory methods
- G06F 12/0822: {Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831)}
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1045: associated with a data cache
- G06F 13/1668: {Details of memory controller}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

## Claims

### Claim 1

An integrated circuit for a coherent data processing system including a system memory, the integrated circuit comprising:
a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;
a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;
a real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory; and
request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface, wherein the request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides the accelerator unit a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein:
the real address-based directory is a set-associative cache directory; and
the host tag specifies the entry in the real address-based directory by entry number.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein:
the integrated circuit of claim 1;
the accelerator unit coupled to the integrated circuit via the second communication interface, wherein:
the accelerator cache includes a cache array and an effective address-based directory of contents of the cache array; and
the accelerator unit includes a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of entries in the accelerator cache.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the accelerator unit is configured to, based on the request response, build a link in the effective address-based directory between a second entry for the second effective address and a first entry for the first effective address.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the accelerator unit is configured to service a memory access request targeting the second effective address by reference to a cache line held in the first entry of the accelerator cache.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the accelerator cache is configured to maintain, in the first entry, both a coherence state field associated with the first effective address and an indication of modification of the cache line by a memory access request referencing the second effective address.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the accelerator cache is configured to silently evict contents of the second entry and configured to, upon castout of the first entry, transmit the cache line to the integrated circuit regardless of whether the coherence state field indicates the cache line is unmodified.

### Claim 8

A method of data processing in a coherent data processing system including a system memory, the method comprising:
host attach logic communicating memory access requests with the coherent data processing system via a first communication interface and communicating, via a second communication interface, memory access requests and request responses with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory;
the host attach logic recording, in a real address-based directory inclusive of contents of the accelerator cache, data from the system memory accessed by the accelerator unit, wherein the recording includes assigning entries in the real address-based directory based on real addresses utilized to identify storage locations in the system memory; and
the host attach logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, providing the accelerator unit a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
the real address-based directory is a set-associative cache directory; and
the host tag specifies the entry in the real address-based directory by entry number.

### Claim 10 (depends on 8)

The method of claim 8, wherein:
the accelerator cache includes a cache array and an effective address-based directory of contents of the cache array; and
the method further comprises the accelerator unit maintaining a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of entries in the accelerator cache.

### Claim 11 (depends on 10)

The method of claim 10, and further comprising:
the accelerator unit, based on the request response, building a link in the effective address-based directory between a second entry for the second effective address and a first entry for the first effective address.

### Claim 12 (depends on 11)

The method of claim 11, and further comprising:
the accelerator cache servicing a memory access request targeting the second effective address by reference to a cache line held in the first entry of the accelerator cache.

### Claim 13 (depends on 12)

The method of claim 12, and further comprising:
the accelerator cache maintaining, in the first entry, both a coherence state field associated with the first effective address and an indication of modification of the cache line by a memory access request referencing the second effective address.

### Claim 14 (depends on 13)

The method of claim 13, and further comprising:
the accelerator cache silently evicting contents of the second entry; and
the accelerator cache, upon castout of the first entry, transmitting the cache line to the integrated circuit regardless of whether the coherence state field indicates the cache line is unmodified.

### Claim 15

A design structure tangibly embodied in a storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
host attach logic for a coherent data processing system including a system memory, the host attach logic including:
a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;
a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;
a real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory; and
request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface, wherein the request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides the accelerator unit a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

### Claim 16 (depends on 15)

The design structure of claim 15, wherein:
the real address-based directory is a set-associative cache directory; and
the host tag specifies the entry in the real address-based directory by entry number.

### Claim 17 (depends on 15)

The design structure of claim 15, and further comprising:
the accelerator unit coupled to the integrated circuit via the second communication interface, wherein:
the accelerator cache includes a cache array and an effective address-based directory of contents of the cache array; and
the accelerator unit includes a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of entries in the accelerator cache.

### Claim 18 (depends on 17)

The design structure of claim 17, wherein the accelerator unit is configured to, based on the request response, build a link in the effective address-based directory between a second entry for the second effective address and a first entry for the first effective address.

### Claim 19 (depends on 18)

The design structure of claim 18, wherein the accelerator unit is configured to service a memory access request targeting the second effective address by reference to a cache line held in the first entry of the accelerator cache.

### Claim 20 (depends on 19)

The design structure of claim 19, wherein the accelerator cache is configured to maintain, in the first entry, both a coherence state field associated with the first effective address and an indication of modification of the cache line by a memory access request referencing the second effective address.