# US 11,030,108 B2 · System, apparatus and method for selective enabling of locality-based instruction handling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,108 B2 - Document ID: US11030108B2 - Status: Granted - Kind: B2 - Application number: 16/540,163 - Filed: 2019-08-14 - Published: 2019-12-05 - Granted: 2021-06-08 - Earliest claimed: 2017-03-31 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Berkin Akin; Rajat Agarwal; Jong Soo Park; Christopher J. Hughes; Chiachen Chou - Web page: https://patentgrep.com/patent/US11030108B2 ## CPC - G06F 12/0888: using selective caching, e.g. bypass - G06F 12/04: Addressing variable-length words or parts of words - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/0886: Variable-length word access - G06F 2212/1024: Latency reduction - G06F 2212/1028: Power efficiency - G06F 2212/283: Plural cache memories - G06F 2212/6046: Using a specific cache allocation policy other than replacement policy - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed. ## Claims ### Claim 1 A processor comprising: a core to receive a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; a buffer having a plurality of entries each to store, for a memory access instruction to a particular address, information including address information; a cache hierarchy; and a memory controller coupled to the core, the memory controller to issue requests to a memory, the memory controller including a locality controller to receive the memory access instruction having the no-locality hint and override the no-locality hint to store the data in the cache hierarchy, based at least in part on the information stored in an entry of the buffer. ### Claim 2 (depends on 1) The processor of claim 1, wherein the no-locality hint is to cause a return of data to the core that bypasses a cache memory of the cache hierarchy of the processor. ### Claim 3 (depends on 1) The processor of claim 1, wherein in response to the override of the no-locality hint, the memory controller is to cause a full width data portion to be obtained from the memory and provided to the core. ### Claim 4 (depends on 1) The processor of claim 1, wherein in response to the no-locality hint, the memory controller is to cause a sub-cache line data portion to be obtained from the memory and provided to the core. ### Claim 5 (depends on 4) The processor of claim 4, wherein the sub-cache line data portion comprises less than a quarter of a cache line. ### Claim 6 (depends on 4) The processor of claim 4, wherein the sub-cache line data portion comprises a single data element. ### Claim 7 (depends on 1) The processor of claim 1, wherein the buffer comprises one of a bypassed address filter and a read combining buffer. ### Claim 8 (depends on 7) The processor of claim 7, wherein when the buffer comprises the read combining buffer, the plurality of entries of the buffer are to store sub-cache line data. ### Claim 9 (depends on 1) The processor of claim 1, wherein the buffer comprises a sparse access buffer. ### Claim 10 (depends on 1) The processor of claim 1, wherein the information comprises confidence information, and the locality controller is to override the no-locality hint when the confidence information exceeds a threshold value. ### Claim 11 (depends on 1) The processor of claim 1, wherein the memory controller is to insert an entry in the buffer in response to a miss in the cache hierarchy of the processor of a second memory access instruction having the no-locality hint. ### Claim 12 (depends on 1) The processor of claim 1, wherein the memory controller comprises the buffer. ### Claim 13 (depends on 1) The processor of claim 1, wherein the memory access instruction comprises a streaming load instruction. ### Claim 14 A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine, cause the machine to perform a method comprising: in response to a miss of a memory access request having a no-locality hint in a cache hierarchy of a processor, determining if the memory access request hits in a buffer associated with a memory controller, the buffer to store information associated with memory access requests having no-locality hints; and if the memory access request hits in the buffer and a confidence value of a hit entry of the buffer exceeds a threshold returning a full width of data to the processor, and otherwise returning a partial width of data of the processor. ### Claim 15 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the method further comprises if the memory access request hits in the buffer and the confidence value of the hit entry of the buffer is less than the threshold, updating the confidence value of the hit entry. ### Claim 16 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the method further comprises returning the partial width of data from the buffer directly to the processor without communication with the memory. ### Claim 17 (depends on 16) The non-transitory machine-readable medium of claim 16, wherein the method further comprises returning the partial width of data to the processor via a bypass path that bypasses the cache hierarchy of the processor. ### Claim 18 A system comprising: a processor having a cache hierarchy including one or more cache memories and a core to process a first memory access instruction having a no-locality hint to indicate non-locality of data associated with the first memory access instruction; a memory controller to issue requests to a system memory, the memory controller including a locality controller to receive the first memory access instruction and to selectively handle the first memory access instruction with locality based at least in part on a locality prediction for the first memory access instruction, wherein in response to a second memory access instruction having the no-locality hint, the memory controller is to issue a request to the system memory for a partial width of data and bypass storage of the partial width of data in the cache hierarchy; and the system memory coupled to the memory controller. ### Claim 19 (depends on 18) The system of claim 18, further comprising a buffer having a plurality of entries each to store, for a memory access instruction to a particular address, address information and a confidence value, wherein the memory controller is to generate the locality prediction based at least in part on the confidence value. ### Claim 20 (depends on 18) The system of claim 18, wherein in response to the selective handle of the first memory access instruction with locality, the memory controller is to issue a request to the system memory for a full width of the data and store the full width of the data in the cache hierarchy.