# US 11,030,103 B2 · Data coherency manager with mapping between physical and virtual address spaces > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,103 B2 - Document ID: US11030103B2 - Status: Granted - Kind: B2 - Application number: 15/922,380 - Filed: 2018-03-15 - Published: 2019-08-29 - Granted: 2021-06-08 - Earliest claimed: 2018-02-28 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: Martin John Robinson; Mark Landers - Web page: https://patentgrep.com/patent/US11030103B2 ## CPC - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence) - G06F 12/10: Address translation - G06F 12/1018: involving hashing techniques, e.g. inverted page tables - G06F 12/1063: {the data cache being concurrently virtually addressed} - G06F 2212/62: Details of cache specific to multiprocessor cache arrangements - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination. ## Claims ### Claim 1 A coherency manager for receiving physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory addressable using a virtual address space, the cache memory having a plurality of virtually addressed coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a physically addressed snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination. ### Claim 2 (depends on 1) The coherency manager according to claim 1, in which the reverse translation module comprises one or both of: logic that calculates the virtual address in dependence on the physical address, based on a known relationship between the physical address space and the virtual address space, and a reverse translation data structure configured to maintain a mapping from the physical address space to the virtual address space. ### Claim 3 (depends on 2) The coherency manager according to claim 2, in which the reverse translation data structure comprises a directory linking a physical address in the physical address space to a corresponding virtual address in the virtual address space. ### Claim 4 (depends on 1) The coherency manager according to claim 1, in which the coherency manager is configured, on determining that the reverse translation module does not comprise a mapping from the physical address to the virtual address space, to cause a response to the snoop request to be sent without accessing the cache memory. ### Claim 5 (depends on 1) The coherency manager according to claim 1, in which the coherency manager is configured, on determining that the reverse translation module does comprise a mapping from the physical address to the virtual address space, to access a cache line status data structure configured to store status information relating to cache lines at the cache memory, and to cause a response to the snoop request to be sent in dependence on the stored status information. ### Claim 6 (depends on 5) The coherency manager according to claim 5, in which, where the status information relating to the cache line indicates that the cache line is at least one of: not present, in an invalid state, undergoing spilling, and undergoing a writeback or eviction process, the coherency manager is configured to determine that the snoop request results in a cache miss and to cause a corresponding response to the snoop request to be sent on the bus. ### Claim 7 (depends on 5) The coherency manager according to claim 5, in which, where the status information relating to the cache line indicates that the cache line is present and is in a clean state, the coherency manager is configured to cause the cache line to be evicted without the cache performing a writeback of the data at that cache line to a main memory, the coherency manager being configured to process the snoop request without accessing the cache. ### Claim 8 (depends on 5) The coherency manager according to claim 5, in which, where the status information relating to the cache line indicates that the cache line is present and is in a dirty state, the coherency manager is configured to cause the cache to be accessed to read the cache line for writing the cache line back to a main memory, and to cause the cache line to be evicted from the cache. ### Claim 9 (depends on 2) The coherency manager according to claim 2, in which the reverse translation data structure is configured to store data at page granularity. ### Claim 10 (depends on 5) The coherency manager according to claim 5, in which the cache line status data structure is configured to store the status information at cache line granularity. ### Claim 11 (depends on 5) The coherency manager according to claim 5, in which the cache line status data structure comprises a plurality of RAM instances, and the coherency manager is configured to access more than one of the RAM instances concurrently. ### Claim 12 (depends on 5) The coherency manager according to claim 5, in which the cache line status data structure comprises an entry for at least one coherent cache line which is at a page mapped by the reverse translation data structure. ### Claim 13 (depends on 12) The coherency manager according to claim 12, in which the cache line status data structure comprises a plurality of status bits in respect of the at least one coherent cache line. ### Claim 14 (depends on 5) The coherency manager according to claim 5, in which the snoop processor is configured to monitor a memory bus coupled to the coherency manager for read requests to a main memory, and to cause the status information in the cache line status data structure to be updated in response to the monitored read requests. ### Claim 15 (depends on 1) The coherency manager according to claim 1, in which the snoop processor comprises a buffer for storing received snoop requests. ### Claim 16 (depends on 15) The coherency manager according to claim 15, in which the snoop processor is configured to process snoop requests on the buffer in a different order to that in which the snoop requests were received. ### Claim 17 (depends on 1) The coherency manager according to claim 1, in which the snoop processor comprises control logic for at least one of controlling access to the cache line status data structure, accessing the cache, sending commands to the cache, and issuing responses to snoop requests. ### Claim 18 A method for processing physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory having a plurality of virtually addressed coherent cachelines addressable using a virtual address space, the method comprising: receiving a physically addressed snoop request relating to a physical address; determining, from a mapping from physical addresses to virtual addresses for each coherent cache line held in the cache memory, whether the physical address is mapped to a virtual address; and processing the snoop request in dependence on that determination. ### Claim 19 A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a coherency manager for receiving physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory addressable using a virtual address space, the cache memory having a plurality of virtually addressed coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a physically addressed snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination. ### Claim 20 (depends on 1) The coherency manager according to claim 1, wherein the snoop processor is configured to, in response to the received snoop request, determine whether the physical address is mapped to a virtual address of one of the plurality of coherent cachelines in the reverse translation module.