# US 11,030,102 B2 · Reducing memory cache control command hops on a fabric

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- Number: US 11,030,102 B2
- Document ID: US11030102B2
- Status: Granted
- Kind: B2
- Application number: 16/125,438
- Filed: 2018-09-07
- Published: 2020-03-12
- Granted: 2021-06-08
- Earliest claimed: 2018-09-07
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Harshavardhan Kaushikkar; Rong Zhang Hu; Xiaoming Wang
- Web page: https://patentgrep.com/patent/US11030102B2

## CPC

- G06F 12/0815: Cache consistency protocols
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 2212/1024: Latency reduction
- G06F 2212/608: Details relating to cache mapping
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.

## Claims

### Claim 1

A computing system comprising:
one or more processing units;
one or more memory controllers; and
a communication fabric distinct from the one or more processing units and the one or more memory controllers, wherein the communication fabric comprises a plurality of transaction processing queues, is coupled to the one or more processing units and the one or more memory controllers, and is configured to:
receive, from a first processing unit, a command payload and a data payload of a first write transaction;
store the command payload and the data payload in a given transaction processing queue of the plurality of transaction processing queues; and
prior to moving the command payload and the data payload out of the given transaction processing queue, complete, for the first write transaction:
coherence operations; and
a memory cache lookup of a memory cache accessed independently of the one or more processing units and the one or more memory controllers.

### Claim 2 (depends on 1)

The computing system as recited in claim 1, wherein the communication fabric comprises:
one or more pipelines, wherein each pipeline of the one or more pipelines is configured to:
perform coherence operations; and
perform a lookup of a corresponding memory cache; and
one or more arbiters, wherein a given arbiter of the one or more arbiters is configured to select the first write transaction for arbitration and forward an address of the first write transaction to a given pipeline of the one or more pipelines.

### Claim 3 (depends on 2)

The computing system as recited in claim 2, wherein each arbiter of the one or more arbiters is configured to supply transactions to one pipeline per memory channel.

### Claim 4 (depends on 3)

The computing system as recited in claim 3, wherein each arbiter is configured to select, from transactions in a plurality of transaction processing queues, transactions for processing by a given pipeline.

### Claim 5 (depends on 4)

The computing system as recited in claim 4, wherein there is a single arbiter between the given transaction processing queue and a given memory controller for the first write transaction.

### Claim 6 (depends on 2)

The computing system as recited in claim 2, wherein the communication fabric further comprises a duplicate tag structure per pipeline, and wherein the communication fabric is configured to convey the data payload from the given transaction processing queue to a memory controller responsive to a memory cache lookup for the first write transaction missing and responsive to a tag lookup of a duplicate tag structure missing.

### Claim 7 (depends on 1)

The computing system as recited in claim 1, wherein the communication fabric is further configured to perform the memory cache lookup by searching one or more address tags stored in the memory cache located between a coherence point and a system memory.

### Claim 8

A method comprising:
receiving, by a communication fabric from a first processing unit, a command payload and a data payload of a first write transaction, wherein the communication fabric is distinct from the one or more processing units and the one or more memory controllers;
storing, in a given transaction processing queue of the communication fabric, the command payload and the data payload; and
prior to moving the command payload and the data payload out of the given transaction processing queue, completing, for the first write transaction:
coherence operations; and
a memory cache lookup of a memory cache accessed independently of the one or more processing units and the one or more memory controllers.

### Claim 9 (depends on 8)

The method as recited in claim 8, further comprising:
forwarding, by a given arbiter, an address of the first write transaction to a given pipeline while the command payload and the data payload remain in the given transaction processing queue; and
performing, by the given pipeline, coherence operations and a lookup of a corresponding memory cache while the command payload and the data payload remain in the given transaction processing queue.

### Claim 10 (depends on 9)

The method as recited in claim 9, further comprising supplying, by each arbiter of one or more arbiters, transactions to one pipeline per memory channel.

### Claim 11 (depends on 10)

The method as recited in claim 10, further comprising selecting, from transactions in a plurality of transaction processing queues, transactions for processing by a pipeline.

### Claim 12 (depends on 11)

The method as recited in claim 11, further comprising traversing, by the first write transaction, a single arbiter in between the given transaction processing queue and a given memory controller.

### Claim 13 (depends on 9)

The method as recited in claim 9, further comprising conveying the data payload from the given transaction processing queue to the given memory controller responsive to a memory cache lookup for the first write transaction missing and responsive to a tag lookup of a duplicate tag structure missing.

### Claim 14 (depends on 8)

The method as recited in claim 8, further comprising searching one or more address tags stored in a memory cache located between a coherence point and a system memory to perform the memory cache lookup.

### Claim 15

An apparatus comprising:
one or more functional units; and
a communication fabric distinct from the one or more functional units, wherein the communication fabric comprises a plurality of transaction processing queues, is coupled to the one or more functional units, and comprises circuitry configured to:
receive, from a first processing unit, a command payload and a data payload of a first write transaction;
store the command payload and the data payload in a given transaction processing queue of the plurality of transaction processing queues; and
prior to moving the command payload and the data payload out of the given transaction processing queue, complete, for the first write transaction:
coherence operations; and
a memory cache lookup of a memory cache accessed independently of the one or more processing units and the one or more memory controllers.

### Claim 16 (depends on 15)

The apparatus as recited in claim 15, wherein the communication fabric comprises an arbiter which is configured to select the first write transaction for arbitration and forward an address of the first write transaction to a given pipeline for performing coherence operations and a lookup of a corresponding memory cache.

### Claim 17 (depends on 16)

The apparatus as recited in claim 16, wherein the arbiter is configured to supply transactions to one pipeline per memory channel.

### Claim 18 (depends on 17)

The apparatus as recited in claim 17, wherein the arbiter is further configured to select, from transactions in a plurality of transaction processing queues, transactions for processing by a given pipeline.

### Claim 19 (depends on 16)

The apparatus as recited in claim 16, wherein the communication fabric comprises a duplicate tag structure per pipeline, and wherein each pipeline is configured to perform a duplicate tag lookup while the command payload and the data payload remain in the given transaction processing queue.

### Claim 20 (depends on 15)

The apparatus as recited in claim 15, wherein the communication fabric is further configured to perform the memory cache lookup by searching one or more address tags stored in a memory cache located between a coherence point and a system memory.