# US 11,030,061 B2 · Single and double chip spare

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- Number: US 11,030,061 B2
- Document ID: US11030061B2
- Status: Granted
- Kind: B2
- Application number: 16/525,086
- Filed: 2019-07-29
- Published: 2019-11-21
- Granted: 2021-06-08
- Earliest claimed: 2017-05-19
- Assignees: Hewlett Packard Enterprise Development LP
- Applicants: Hewlett Packard Enterprise Development LP
- Inventors: Gary Gostin; Erin A. Handgen
- Web page: https://patentgrep.com/patent/US11030061B2

## CPC

- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 11/1064: {in cache or content addressable memories}
- G11C 29/808: {using a flexible replacement scheme}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0683: {Plurality of storage devices}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 29/74: {using duplex memories, i.e. using dual copies}
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

## Claims

### Claim 1

A device comprising:
a memory controller to:
access a first portion of a memory, the first portion of the memory operating in single chip spare mode;
access a second portion of the memory, the second portion of the memory operating in double chip spare mode while the first portion is operating in the single chip spare mode;
detect an error in a first region of the first portion of the memory; and
convert the first region containing the error to operate in double chip spare mode, while leaving a second region of the first portion operating in single chip spare mode.

### Claim 2

A device comprising:
a memory controller to:
access a first portion of a memory, the first portion of the memory operating in single chip spare mode;
access a second portion of the memory, the second portion of the memory operating in double chip spare mode while the first portion is operating in the single chip spare mode;
detect an error in a first region of the first portion of the memory;
select a second region in the first portion of the memory, the second region equal in size to the first region; and
convert cache lines between the first and second regions to form a third region, the third region operating in double chip spare mode.

### Claim 3 (depends on 2)

The device of claim 2 wherein the first and second regions of the memory are on a single memory bus.

### Claim 4 (depends on 2)

The device of claim 2 wherein the first region is on a first memory bus and the second region is on a second memory bus.

### Claim 5

A method comprising:
detecting a single chip error in a first region of memory, the first region of memory operating in single chip spare mode;
selecting a second region of memory equal in size to the first region of memory, the second region of memory operating in single chip spare mode; and
converting the first and second region of memory from single chip spare mode to double chip spare mode; wherein, after converting, a third region of memory is operated in single chip spare mode while the first and second region of memory are in double chip spare mode.

### Claim 6 (depends on 5)

The method of claim 5 wherein converting the first and second region of memory further comprises:
computing a double chip spare error correction code for cache lines in the first and second regions of memory; and
storing the cache lines and the computed error correction codes into the first and second regions of memory, wherein each cache line and computed error correction code spans the first and second region of memory.

### Claim 7 (depends on 6)

The method of claim 6 further comprising:
determining a first double chip spare base, the first double chip spare base identifying the beginning of the first region of memory;
determining a first double chip spare limit, the double chip spare limit identifying the end of the first region of memory;
determining a second double chip spare base, the second double chip spare base identifying the beginning of the second region of memory;
determining a second double chip spare limit, the second double chip spare limit identifying the end of the second region of memory;
setting conversion pointers to point to the first and second double chip spare bases; and
while the conversion pointers are less than the first and second double chip spare limits:
read cache lines pointed to by the conversion pointers and correct any errors using single chip spare error correction codes; and
advancing the conversion pointers to a next cache line in the first and second regions.

### Claim 8 (depends on 7)

The method of claim 7 wherein access of cache lines above the double chip spare bases and below the conversion pointers are in double chip spare mode.

### Claim 9 (depends on 7)

The method of claim 7 wherein access of cache lines above the conversion pointers and below the double chip spare limits are in single chip spare mode.

### Claim 10 (depends on 7)

The method of claim 7 wherein access of the cache lines pointed to by the conversion pointers is rejected and retried at a later time.

### Claim 11

A method comprising:
detecting an error in a portion of a memory operating in single chip spare mode;
determining a first region of the memory that is affected by the error; and
converting the first region to operate in double chip spare mode; and
leaving a second region of the memory operating in single chip spare mode.

### Claim 12 (depends on 11)

The method of claim 11 wherein converting the first region further comprises:
determining a third region of the memory equal in size to the first region, the third region containing no errors and operating in the single chip spare mode;
calculating a double chip spare error correction code for each cache line in the first and third regions;
storing each cache line and calculated error correction code in a combined region comprising the first and third regions.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
detecting a second single chip error in the combined region, the second error occurring in the second region;
converting the combined region back into the first memory region and the second memory region, wherein the first and second regions operate in the single chip spare mode;
determining a fourth region of the memory equal in size to the first region, the fourth region containing no errors and operating in the single chip spare mode;
calculating a double chip spare error correction code for each cache line in the first and fourth regions;
storing each cache line and calculated error correction code in a combined region comprising the first and fourth regions.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
determining a fifth region of the memory equal in size to the second region, the fifth region containing no errors and operating in the single chip spare mode;
calculating a double chip spare error correction code for each cache line in the second and fifth regions;
storing each cache line and calculated error correction code in a combined region comprising the second and fifth regions.