# US 11,030,040 B2 · Memory device detecting an error in write data during a write operation, memory system including the same, and operating method of memory system

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- Number: US 11,030,040 B2
- Document ID: US11030040B2
- Status: Granted
- Kind: B2
- Application number: 16/027,767
- Filed: 2018-07-05
- Published: 2019-01-10
- Granted: 2021-06-08
- Earliest claimed: 2017-07-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hoiju Chung; Young-Do Hur; Hyuk Lee; Jang-Ryul Kim
- Web page: https://patentgrep.com/patent/US11030040B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.

## Claims

### Claim 1

A memory device comprising:
a write error check circuit suitable for detecting an error in received data, transferred from a memory controller, using a received error correction code, transferred from the memory controller, during a write operation; and
a memory core suitable for storing the received data and the received error correction code that is used for detecting the error in the received data when no error is detected by the write error check circuit,
wherein, when an error in the received data is detected by the write error check circuit during the write operation, the received error correction code and the received data are not stored in the memory core.

### Claim 2 (depends on 1)

The memory device according to claim 1, further comprising:
an in-memory error correction circuit suitable for, during a read operation, checking for an error in data read from the memory core using the error correction code read from the memory core, and correcting the error in the read data using the read error correction code when the error in the read data is between one bit and N bits inclusive, where N is an integer of 1 or more.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein a maximum bit number of an error that is correctable using the error correction code is M bits, where M is an integer greater than N.

### Claim 4 (depends on 2)

The memory device according to claim 2, wherein the error correction code includes a cyclic redundancy check (CRC) code and a simple parity code.

### Claim 5 (depends on 2)

The memory device according to claim 2, wherein the memory device is a high bandwidth memory (HBM).

### Claim 6 (depends on 1)

The memory device according to claim 1,
wherein, when an error in the received data is detected by the write error check circuit, the memory device notifies a memory controller that the error is detected.

### Claim 7

A memory system including a memory device and a memory controller,
the memory device comprising:
a write error check circuit suitable for detecting an error in data, received from the memory controller using an error correction code received from the memory controller during a write operation; and
a memory core suitable for storing the received data and the received error correction code that is used for detecting the error in the data when no error is detected by the write error check circuit,
the memory controller comprising:
an error correction code generation circuit suitable for generating the error correction code to be transferred to the memory device using the data to be transferred to the memory device; and
an error correction circuit suitable for correcting, when an error is present in data transferred from the memory device, the error in the data transferred using an error correction code transferred from the memory device,
wherein, when an error in the received data is detected by the write error check circuit during the write operation, the received error correction code and the received data are not stored in the memory core.

### Claim 8 (depends on 7)

The memory device according to claim 7, wherein the memory device further comprises:
an in-memory error correction circuit suitable for, during a read operation, checking for an error in data read from the memory core using an error correction code read from the memory core, and correcting the error in the read data using the read error correction code when the error in the read data is between one bit and N bits inclusive, where N is an integer of 1 or more.

### Claim 9 (depends on 8)

The memory device according to claim 8, wherein the error correction circuit has error correction capability of M bits, where M is an integer greater than N.

### Claim 10 (depends on 7)

The memory device according to claim 7,
wherein, when an error in the received data is detected by the write error check circuit, the received error correction code and the received data are not stored in the memory core, and
wherein the memory device notifies the memory controller that the error is detected.

### Claim 11 (depends on 7)

The memory device according to claim 7, wherein the memory device writes a codeword corresponding to one write command, and reads a codeword corresponding to one read command.

### Claim 12 (depends on 7)

The memory device according to claim 7, wherein the memory device is a high bandwidth memory (HBM).

### Claim 13 (depends on 7)

The memory device according to claim 7, wherein the error correction code includes a cyclic redundancy check (CRC) code and a simple parity code.

### Claim 14

A method for operating a memory system, comprising:
generating, by a memory controller, an error correction code using write data;
transferring a write command, the write data, and the error correction code to a memory device from the memory controller;
detecting, by the memory device, an error in the write data using the error correction code;
storing, when no error in the write data is detected, the write data and the error correction code that is used for detecting the error in the write data, in a memory core of the memory device; and
not performing a write operation by the memory device and notifying the memory controller that an error in the write data is detected, when the error in the write data is detected.

### Claim 15 (depends on 14)

The method according to claim 14, further comprising:
transferring a read command from the memory controller to the memory device;
reading data and an error correction code from the memory core of the memory device;
detecting, by the memory device, an error in the data read from the memory core using the error correction code read from the memory core;
correcting, when the error in the read data is between one bit and N bits inclusive, where N is an integer of 1 or more, the error in the read data using the read error correction code, and transferring error-corrected data and the read error correction code to the memory controller from the memory device;
transferring, when no error is detected in the read data or the error in the read data exceeds N bits, the read data and the read error correction code to the memory controller from the memory device; and
correcting, by the memory controller, when an error is present in the data transferred from the memory device, the error in the data transferred using the error correction code transferred from the memory device.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the memory controller has error correction capability of M bits, where M is an integer greater than N.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the write data and the error correction code transferred to the memory device are an entire codeword corresponding to the write command transferred to the memory device.

### Claim 18 (depends on 14)

The method according to claim 14, wherein the error correction code includes a cyclic redundancy check (CRC) code and a simple parity code.

### Claim 19 (depends on 14)

The method according to claim 14, wherein the memory device is a high bandwidth memory (HBM).