# US 11,030,030 B2 · Enhanced address space layout randomization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,030,030 B2 - Document ID: US11030030B2 - Status: Granted - Kind: B2 - Application number: 16/259,736 - Filed: 2019-01-28 - Published: 2019-08-01 - Granted: 2021-06-08 - Earliest claimed: 2016-07-02 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Tomer Stark; Ron Gabor; Joseph Nuzman - Web page: https://patentgrep.com/patent/US11030030B2 ## CPC - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - G06F 12/0623: {for memory modules} - G06F 12/14: Protection against unauthorised use of memory {or access to memory} - G06F 2212/1052: Security improvement - G06F 2212/657: Virtual address space management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space. ## Claims ### Claim 1 An enhanced address space memory corruption detection apparatus, comprising: memory circuitry to provide a linear address space that includes a metadata data structure; metadata circuitry to receive a memory access request that includes a target address pointer comprising a target metadata value and target linear address; and metadata comparison circuitry to compare the target metadata value to a metadata value stored in the metadata data structure at a location pointed to by at least a portion of the target linear address; wherein the metadata circuitry is further to, responsive to a determination that the target metadata value and the stored metadata value are identical, grant the memory access request to allow access to the target linear address. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the metadata circuitry is further to: receive a second memory access request that includes a second target address pointer indicating a second target metadata value and a second target linear address; and responsive to a determination that the second target metadata value and a second stored metadata value in the metadata data structure are not identical, prevent access to the second target linear address. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the metadata circuitry is further to, responsive to the determination that the second target metadata value and the second stored metadata value are not identical, generate a fault. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the target address pointer corresponds to an apparent address in an enhanced address space having a size that is greater than a size of the linear address space. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the metadata data structure is a two-level data structure. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein the metadata circuitry is further to, responsive to the determination that the target metadata value and the stored metadata value are identical, modify the target address pointer to remove the target metadata value from the target address pointer. ### Claim 7 (depends on 1) The apparatus of claim 1 wherein the target linear address comprises 48 bits and the target address pointer comprises 64 bits. ### Claim 8 An enhanced address space memory corruption detection method, comprising: receiving, via metadata logic, a memory access request that includes a target address pointer comprising a target metadata value and target linear address; comparing, via the metadata logic, the target metadata value to a metadata value stored in a metadata data structure at a location pointed to by at least a portion of the target linear address, the metadata data structure being included in a linear address space; and responsive to a determination that the target metadata value and the stored metadata value are identical, granting the memory access request to allow access to the target linear address. ### Claim 9 (depends on 8) The method of claim 8, further comprising receiving a second memory access request including a second target address pointer that indicates a second target metadata value and a second target linear address and, responsive to a determination that the second target metadata value and a second stored metadata value in the metadata data structure are not identical, preventing access to the second target linear address. ### Claim 10 (depends on 9) The method of claim 9 further comprising, responsive to the determination that the second target metadata value and the second stored metadata value are not identical, generating a fault. ### Claim 11 (depends on 8) The method of claim 8, wherein the metadata data structure is included in the linear address space, and wherein the target address pointer corresponds to an apparent address in an enhanced address space having a size that is greater than a size of the linear address space. ### Claim 12 (depends on 8) The method of claim 8 wherein the metadata data structure is a two-level data structure. ### Claim 13 (depends on 8) The method of claim 8 further comprising, responsive to the determination that the target metadata value and the stored metadata value are identical, modifying the target address pointer by removing the target metadata value from the target address pointer. ### Claim 14 (depends on 8) The method of claim 8 wherein the target linear address comprises 48 bits and the target address pointer comprises 64 bits. ### Claim 15 An enhanced address space memory corruption detection system, comprising: a processor comprising at least one processor register; memory circuitry to provide a linear address space that includes a metadata data structure; metadata logic to receive a memory access request that includes a target address pointer comprising a target metadata value and target linear address; and metadata comparison logic to compare the target metadata value to a metadata value stored in the metadata data structure at a location pointed to by at least a portion of the target linear address; wherein the metadata logic is further to, responsive to a determination that the target metadata value and the stored metadata value are identical, grant the memory access request to allow access to the target linear address. ### Claim 16 (depends on 15) The system of claim 15, wherein the metadata logic is further to: receive a second memory access request that includes a second target address pointer indicating a second target metadata value and a second target linear address; and responsive to a determination that the second target metadata value and a second stored metadata value in the metadata data structure are not identical, prevent access to the second target linear address. ### Claim 17 (depends on 16) The system of claim 16 wherein the metadata logic is further to, responsive to the determination that the second target metadata value and the second stored metadata value are not identical, generate a fault. ### Claim 18 (depends on 15) The system of claim 15, wherein the target address pointer corresponds to an apparent address in an enhanced address space having a size that is greater than a size of the linear address space. ### Claim 19 (depends on 15) The system of claim 15 wherein the metadata data structure is a two-level data structure. ### Claim 20 (depends on 15) The system of claim 15 wherein the metadata logic is further to, responsive to the determination that the target metadata value and the stored metadata value are identical, modify the target address pointer to remove the target metadata value from the target address pointer. ### Claim 21 (depends on 15) The system of claim 15 wherein the target linear address comprises 48 bits and the target address pointer comprises 64 bits.