# US 11,030,000 B2 · Core advertisement of availability

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- Number: US 11,030,000 B2
- Document ID: US11030000B2
- Status: Granted
- Kind: B2
- Application number: 16/457,966
- Filed: 2019-06-29
- Published: 2020-12-31
- Granted: 2021-06-08
- Earliest claimed: 2019-06-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Elmoustapha Ould-Ahmed-Vall
- Web page: https://patentgrep.com/patent/US11030000B2

## CPC

- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)}
- G06F 2209/503: Resource availability
- G06F 2209/509: Offload
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments involving core-to-core offload are detailed herein. For example, a method comprising: monitoring performance of a first core using performance monitoring circuitry; determining a core-to-core offload availability status of the first core based at least in part on values store in the performance monitoring circuitry; and transmitting an availability indication to a second core of an availability of the first core to act as a helper core to perform one or more tasks on behalf of the second core based upon the determined offload availability status of the first core is described.

## Claims

### Claim 1

A processor comprising:
a plurality of cores including at least a first and a second core;
the first core comprising:
performance monitoring circuitry to monitor performance of the first core,
core-to-core offload circuitry to:
determine an offload availability status of the first core based at least in part on values store in the performance monitoring circuitry, and
transmit an availability indication to the second core of an availability of the first core to act as a helper core to perform one or more tasks on behalf of the second core based upon the determined offload availability status of the first core,
execution circuitry to execute decoded instructions of the one or more tasks of the second core; and
the second core comprising:
execution circuitry to execute decoded instructions of the one or more tasks of the second core, and
an offload phase tracker to maintain status information about at least an availability of the first core to act as a helper core.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the availability indication is to include a type of availability available including one of compute, memory, and input/output.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the availability indication is to be periodically transmitted.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the availability indication is to be transmitted only when there is a determination of a change in the availability of the first core.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the offload phase tracker is to be maintained by a core-to-core finite state machine.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the performance monitoring circuitry is to track events including one or more of:
a number of instructions of any type retired;
a number of unhalted core cycles;
a number of cache misses;
a number of cache access;
a number of branch instructions retired;
a number of branch misses retired; and
a number of available slots.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the indication of the first core to act as a helper core to perform one or more tasks on behalf of the second core is not routed through an operating system.

### Claim 8

A method comprising:
monitoring performance of a first core using performance monitoring circuitry;
determining a core-to-core offload availability status of the first core based at least in part on values store in the performance monitoring circuitry; and
transmitting an availability indication to a second core of an availability of the first core to act as a helper core to perform one or more tasks on behalf of the second core based upon the determined offload availability status of the first core.

### Claim 9 (depends on 8)

The method of claim 8, wherein the availability indication is to include a type of availability available including one of compute, memory, and input/output.

### Claim 10 (depends on 8)

The method of claim 8, wherein the availability indication is to be periodically transmitted.

### Claim 11 (depends on 8)

The method of claim 8, wherein the availability indication is to be transmitted only when there is a determination of a change in the availability of the first core.

### Claim 12 (depends on 8)

The method of claim 8, wherein the offload phase tracker is to be maintained by a core-to-core finite state machine.

### Claim 13 (depends on 8)

The method of claim 8, wherein the performance monitoring circuitry is to track events including one or more of:
a number of instructions of any type retired;
a number of unhalted core cycles;
a number of cache misses;
a number of cache access;
a number of branch instructions retired;
a number of branch misses retired; and
a number of available slots.

### Claim 14 (depends on 8)

The method of claim 8, wherein the indication of the first core to act as a helper core to perform one or more tasks on behalf of the second core is not routed through an operating system.

### Claim 15

A system comprising:
a memory to store an offload task;
a plurality of cores including at least a first and a second core;
the first core comprising:
performance monitoring circuitry to monitor performance of the first core,
core-to-core offload circuitry to:
determine an offload availability status of the first core to handle the stored offload task based at least in part on values store in the performance monitoring circuitry, and
transmit an availability indication to the second core of an availability of the first core to act as a helper core to perform one or more tasks on behalf of the second core based upon the determined offload availability status of the first core,
execution circuitry to execute decoded instructions of the one or more tasks of the second core; and
the second core comprising:
execution circuitry to execute decoded instructions of the one or more tasks of the second core, and
an offload phase tracker to maintain status information about at least an availability of the first core to act as a helper core.

### Claim 16 (depends on 1)

The system of claim 1, wherein the availability indication is to include a type of availability available including one of compute, memory, and input/output.

### Claim 17 (depends on 1)

The system of claim 1, wherein the availability indication is to be periodically transmitted.

### Claim 18 (depends on 1)

The system of claim 1, wherein the availability indication is to be transmitted only when there is a determination of a change in the availability of the first core.

### Claim 19 (depends on 1)

The system of claim 1, wherein the offload phase tracker is to be maintained by a core-to-core finite state machine.

### Claim 20 (depends on 1)

The system of claim 1, wherein the indication of the first core to act as a helper core to perform one or more tasks on behalf of the second core is not routed through an operating system.