# US 11,029,960 B2 · Apparatus and method for widened SIMD execution within a constrained register file > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,960 B2 - Document ID: US11029960B2 - Status: Granted - Kind: B2 - Application number: 16/214,012 - Filed: 2018-12-07 - Published: 2020-06-11 - Granted: 2021-06-08 - Earliest claimed: 2018-12-07 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Marek Targowski; Konrad Trifunović - Web page: https://patentgrep.com/patent/US11029960B2 ## CPC - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30065: {Loop control instructions; iterative instructions, e.g. LOOP, REPEAT} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/30101: {Special purpose registers} - G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Apparatus and method for widened SIMD execution on a limited register file. For example, one embodiment of an apparatus comprises: instruction dispatch circuitry to dispatch instructions of a thread for execution, including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and execution circuitry including single instruction multiple data (SIMD) circuitry, the execution circuitry to execute the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry and to execute the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry. ## Claims ### Claim 1 An apparatus comprising: instruction dispatch circuitry to dispatch instructions of a thread for execution, including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and execution circuitry including single instruction multiple data (SIMD) circuitry, the execution circuitry to execute the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry and to execute the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry without the first and second sets of lanes being overlapped, and wherein, in response to executing the second instruction for a first number of times, the execution circuitry is to execute the double execution instruction sequence using the second set of lanes of the SIMD circuitry, and in response to executing the second instruction for a second number of times, the execution circuitry is to execute further instructions using both first and second sets of lanes. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the execution circuitry, in response to execution of the first instruction, is to set a first per-thread context and a first execution mask value for the first pass. ### Claim 3 (depends on 2) The apparatus of claim 2 wherein the execution circuitry, in response to a first execution of the second instruction, is to set a second per-thread context and a second execution mask value for the second pass. ### Claim 4 (depends on 3) The apparatus of claim 3 wherein the first execution mask is to specify execution on the first set of lanes and the second execution mask is to specify execution on the second set of lanes. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the first set of lanes comprises a first half of one or more SIMD registers and the second set of lanes comprises a second half of the one or more SIMD registers. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein the execution circuitry, in response to execution of the second instruction, is to jump to the start of the double execution instruction sequence in response to a control value associated with the second instruction having a first value. ### Claim 7 (depends on 6) The apparatus of claim 6 wherein the execution circuitry, in response to execution of the second instruction, is to allow execution of instructions following the second instruction. ### Claim 8 (depends on 1) The apparatus of claim 1 wherein the execution circuitry comprises one of a plurality of execution units of a graphics processor and wherein the double execution instruction sequence comprises instructions of a graphics Kernel. ### Claim 9 (depends on 1) The apparatus of claim 1 wherein the first instruction and the second instruction are inserted by a compiler based on register pressure associated with the double execution instruction sequence. ### Claim 10 A method comprising: dispatching instructions of a thread for execution, the instructions including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and executing on single instruction multiple data (SIMD) circuitry the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry; executing the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry without the first and second sets of lanes being overlapped, in response to executing the second instruction for a first number of times; and executing further instructions using both first and second sets of lanes, in response to executing the second instruction for a second number of times. ### Claim 11 (depends on 10) The method of claim 10 further comprising: setting a first per-thread context and a first execution mask value for the first pass in response to the first instruction. ### Claim 12 (depends on 11) The method of claim 11 further comprising: setting a second per-thread context and a second execution mask value for the second pass in response to the second instruction. ### Claim 13 (depends on 12) The method of claim 12 wherein the first execution mask is to specify execution on the first set of lanes and the second execution mask is to specify execution on the second set of lanes. ### Claim 14 (depends on 10) The method of claim 10 wherein the first set of lanes comprises a first half of one or more SIMD registers and the second set of lanes comprises a second half of the one or more SIMD registers. ### Claim 15 (depends on 10) The method of claim 10 further comprising: jumping to the start of the double execution instruction sequence in response to a control value associated with the second instruction having a first value. ### Claim 16 (depends on 15) The method of claim 15 further comprising: allowing execution of instructions following the second instruction in response to the control value having a second value. ### Claim 17 (depends on 10) The method of claim 10 wherein the dispatching and executing is to be performed on execution units of a graphics processor and wherein the double execution instruction sequence comprises instructions of a graphics Kernel. ### Claim 18 (depends on 10) The method of claim 10 wherein the first instruction and the second instruction are inserted by a compiler based on register pressure associated with the double execution instruction sequence. ### Claim 19 A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: dispatching instructions of a thread for execution, the instructions including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and executing on single instruction multiple data (SIMD) circuitry the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry; executing the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry without the first and second sets of lanes being overlapped, in response to executing the second instruction for a first number of times; and executing further instructions using both first and second sets of lanes, in response to executing the second instruction for a second number of times. ### Claim 20 (depends on 19) The non-transitory machine-readable medium of claim 19 further comprising program code to cause the machine to perform the operations of: setting a first per-thread context and a first execution mask value for the first pass in response to the first instruction. ### Claim 21 (depends on 20) The non-transitory machine-readable medium of claim 20 further comprising program code to cause the machine to perform the operations of: setting a second per-thread context and a second execution mask value for the second pass in response to the second instruction. ### Claim 22 (depends on 21) The non-transitory machine-readable medium of claim 21 wherein the first execution mask is to specify execution on the first set of lanes and the second execution mask is to specify execution on the second set of lanes. ### Claim 23 (depends on 19) The non-transitory machine-readable medium of claim 19 wherein the first set of lanes comprises a first half of one or more SIMD registers and the second set of lanes comprises a second half of the one or more SIMD registers. ### Claim 24 (depends on 19) The non-transitory machine-readable medium of claim 19 further comprising program code to cause the machine to perform the operations of: jumping to the start of the double execution instruction sequence in response to a control value associated with the second instruction having a first value. ### Claim 25 (depends on 24) The non-transitory machine-readable medium of claim 24 further comprising program code to cause the machine to perform the operations of: allowing execution of instructions following the second instruction in response to the control value having a second value. ### Claim 26 (depends on 19) The non-transitory machine-readable medium of claim 19 wherein the dispatching and executing is to be performed on execution units of a graphics processor and wherein the double execution instruction sequence comprises instructions of a graphics Kernel. ### Claim 27 (depends on 19) The non-transitory machine-readable medium of claim 19 wherein the first instruction and the second instruction are inserted by a compiler based on register pressure associated with the double execution instruction sequence.