# US 11,029,956 B2 · Processor and information processing system for instructions that designate a circular buffer as an operand > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,956 B2 - Document ID: US11029956B2 - Status: Granted - Kind: B2 - Application number: 16/639,228 - Filed: 2018-07-06 - Published: 2020-06-25 - Granted: 2021-06-08 - Earliest claimed: 2017-08-24 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Hiroshi Kobayashi - Web page: https://patentgrep.com/patent/US11029956B2 ## CPC - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30134: {Register stacks; shift registers} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Data is supplied in a circular manner and overlapping memory accesses is suppressed in a processor. The processor includes a circular buffer and an instruction executing part. The circular buffer has a function of holding a plurality of pieces of data and reading the plurality of pieces of data in circulation. The instruction executing part executes an instruction that designates the circular buffer as an operand. That is, this processor has an instruction that designates the circular buffer as an operand, as an instruction set. With this configuration, the data is supplied in a circular manner from the circular buffer in the execution of the instruction by the processor. ## Claims ### Claim 1 A processor, comprising: a first circular buffer that includes: a shift register that includes a plurality of shift selectors and a plurality of specific registers at a plurality of stages, wherein each specific register of the plurality of specific registers and each shift selector of the plurality of shift selectors correspond to a respective stage of the plurality of stages, a specific register of the plurality of specific registers is configured to output first data to a first shift selector of the plurality of shift selectors and a second shift selector of the plurality of shift selectors, the specific register and the first shift selector are in a first stage of the plurality of stages, and the second shift selector is in a second stage of the plurality of stages; and a circulation selector configured to one of input new data to the shift register or circulate the first data; and an instruction executing part configured to execute an instruction that designates the first circular buffer as an operand. ### Claim 2 (depends on 1) The processor according to claim 1, wherein the instruction executing part includes a load store unit, and the load store unit is configured to one of: load second data from a memory into the first circular buffer, or store the first data to the memory. ### Claim 3 (depends on 2) The processor according to claim 2, wherein the load store unit is further configured to load the second data into the circulation selector. ### Claim 4 (depends on 1) The processor according to claim 1, wherein the instruction executing part includes an operation unit, and the operation unit is configured to execute an operation based on the first circular buffer as the operand. ### Claim 5 (depends on 4) The processor according to claim 4, further comprising a plurality of circular buffers configured to hold a plurality of pieces of data, wherein the operation unit is further configured to execute the operation between the plurality of pieces of data held in the plurality of circular buffers. ### Claim 6 (depends on 5) The processor according to claim 5, wherein the operation unit is further configured to execute a multiply-add operation between the plurality of pieces of data held in the plurality of circular buffers. ### Claim 7 (depends on 5) The processor according to claim 5, wherein the first circular buffer is configured to hold a filter coefficient, a second circular buffer of the plurality of circular buffers is configured to hold target data, and the operation unit is further configured to: execute a filter operation between the filter coefficient and the target data; cause a third circular buffer of the plurality of circular buffers to hold an operation result of the filter operation. ### Claim 8 (depends on 4) The processor according to claim 4, further comprising a general-purpose register configured to hold second data, wherein the first circular buffer is configured to hold third data, and the operation unit is further configured to execute the operation on the second data and the third data. ### Claim 9 (depends on 1) The processor according to claim 1, wherein the instruction executing part includes a data transfer unit, and the data transfer unit is configured to transfer second data between the first circular buffer and a general-purpose register. ### Claim 10 An information processing system, comprising: a memory; a circular buffer configured to load specific data from the memory, wherein the circular buffer includes: a shift register that includes a plurality of shift selectors and a plurality of specific registers at a plurality of stages, wherein each specific register of the plurality of specific registers and each shift selector of the plurality of shift selectors correspond to a respective stage of the plurality of stages, a specific register of the plurality of specific registers is configured to output the specific data to a first shift selector of the plurality of shift selectors and a second shift selector of the plurality of shift selectors, the specific register and the first shift selector are in a first stage of the plurality of stages, and the second shift selector is in a second stage of the plurality of stages; and a circulation selector configured to one of input new data to the shift register or circulate the specific data; and an instruction executing part configured to execute an instruction that designates the circular buffer as an operand.