# US 11,029,954 B2 · Per-lane dynamic indexing in temporary registers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,954 B2 - Document ID: US11029954B2 - Status: Granted - Kind: B2 - Application number: 16/445,199 - Filed: 2019-06-18 - Published: 2020-10-22 - Granted: 2021-06-08 - Earliest claimed: 2019-04-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Wilson Wai Lun Fung; Mrinal Deo - Web page: https://patentgrep.com/patent/US11029954B2 ## CPC - G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file} - G06F 9/30138: {Extension of register space, e.g. register cache} - G06F 9/35: Indirect addressing - G06F 9/355: Indexed addressing - G06F 9/3824: {Operand accessing} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters} - G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one general aspect, an apparatus may include execution unit circuits, each configured to access one or more pieces of data. The apparatus may include local register file circuits, each associated with a respective execution unit circuit and each configured to store data. The apparatus may include a main register circuit. The main register circuit may include a main register file circuit configured to store data. The main register circuit may include a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits. The main register circuit may be configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location of the specified data. ## Claims ### Claim 1 An apparatus comprising: one or more execution unit circuits, each configured to access one or more pieces of data; one or more local register file circuits, each associated with a respective execution unit circuit and each configured to store data for the respective execution unit; and a main register circuit comprising: a main register file circuit configured to store data that is shared by the execution unit circuits, and a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits, and wherein the main register circuit is configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location for the specified data. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the local register file circuit(s) has an index-based storage location system, and wherein each of the local register file circuit(s) is configured to access a piece of data independently of an active index of the other local register file circuit(s). ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the apparatus comprises a hierarchical register file circuit, wherein the hierarchical register file circuit comprises the main register file circuit and the one or more local register file circuits. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the executions unit circuits comprise arithmetic logic unit (ALU) circuits. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the main register file is shared between the one or more execution unit circuits. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising the control circuit, wherein the control circuit is configured to allocate a single-instruction, multiple data (SIMD) instruction to at least a subset of the one or more execution unit circuits, and, as operands of the SIMD instruction, request access to pieces of data for the execution unit circuits. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the operand of the SIMD instruction includes a direct reference to the storage location in the plurality of local register files. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein each of the local register file circuits' storage locations are determined by an index value that is determined and maintained without regard to the other local register file circuits' index value. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the main register circuit is configured to determine the target local register file circuit's storage location of the piece of data by only accessing the local index register circuit and without accessing an off-core memory. ### Claim 10 A system comprising: a processor core comprising: one or more execution unit circuits, each configured to access one or more pieces of data; one or more local register file circuits, each associated with a respective execution unit and each configured to store data; and a main register circuit, the main register circuit comprising a local index register circuit configured to store, for each local register file, an active index value, and wherein configured to, in response to a request from a control circuit to access a target execution unit circuit, supply the active index value associated with the target execution unit circuit; and an off-core memory circuit configured to store data. ### Claim 11 (depends on 10) The system of claim 10, wherein each of the one or more local register file circuits is configured to access, via the respective local register file circuit's active index value, a piece of data independently of the active index values of the other local register file circuits. ### Claim 12 (depends on 10) The system of claim 10, wherein the processor core comprises a hierarchical register file circuit, wherein the hierarchical register file circuit comprises a main register file circuit and the one or more local register file circuits. ### Claim 13 (depends on 10) The system of claim 10, further comprising the control circuit, wherein the control circuit is configured to determine if an instruction is of a first type or a second type, if the instruction is of the first type, compute an operand employing the off-core memory circuit, and if the instruction is of the second type, directly request an active index from the main register circuit. ### Claim 14 (depends on 10) The system of claim 10, wherein the main register circuit comprising a main register file that is shared between the one or more execution unit circuits. ### Claim 15 (depends on 10) The system of claim 10, further comprising the control circuit, wherein the control circuit is configured to allocate a single-instruction, multiple data (SIMD) instruction to at least a subset of the plurality of execution unit circuits, and, as operands of the SIMD instruction, request access to data for the execution unit circuits. ### Claim 16 (depends on 15) The system of claim 15, wherein the operand of the SIMD instruction includes a direct reference to the storage location in the one or more local register files. ### Claim 17 (depends on 10) The system of claim 10, wherein each of the local register file circuits' storage locations are determined by an index value that is determined and maintained without regard to the other local register file circuits' index value. ### Claim 18 (depends on 10) The system of claim 10, wherein the main register circuit is configured to determine the target local register file circuit's storage location of the piece of data by only accessing the local index register circuit and without accessing the off-core memory circuit. ### Claim 19 An apparatus comprising: a plurality of execution unit circuits, each configured to access one or more pieces of data; a plurality of local register file circuits, each associated with a respective execution unit and each configured to store pieces of data; and a main register circuit comprising: a main register file circuit configured to store data for at least part of the plurality of execution unit circuits, and a local index register circuit configured to identify an active storage location in the plurality of local register files, and a control circuit configured to: issue an instruction to a target execution unit circuit, and instruct the local index register circuit to access, at the active storage location, the local register file associated with the target execution unit circuit. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein each of the local register file circuits' storage locations are determined by an index value that is determined and maintained without regard to the other local register file circuits' index value.