# US 11,029,953 B2 · Branch prediction unit in service of short microcode flows > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,953 B2 - Document ID: US11029953B2 - Status: Granted - Kind: B2 - Application number: 16/453,704 - Filed: 2019-06-26 - Published: 2020-12-31 - Granted: 2021-06-08 - Earliest claimed: 2019-06-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Michael Mishaeli; Ido Ouziel; Jared Warner Stark, IV - Web page: https://patentgrep.com/patent/US11029953B2 ## CPC - G06F 9/30065: {Loop control instructions; iterative instructions, e.g. LOOP, REPEAT} - G06F 9/30018: {Bit or string instructions} - G06F 9/30038: {using a mask} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30058: {Conditional branch instructions} - G06F 9/30098: {Register arrangements} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30196: {using decoder, e.g. decoder per instruction set, adaptable or programmable decoders} - G06F 9/323: {for indirect branch instructions} - G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F 12/12: Replacement control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows. ## Claims ### Claim 1 A processor comprising: a branch prediction unit (BPU): and a pipeline comprising: a fetch stage to fetch an instruction specifying an opcode, an operand that is a string, and a length of the string, wherein the BPU is to generate a hint reflecting a predicted result of whether the length of the string is shorter than a threshold; a decode stage to generate a micro-operation flow comprising a first flow when the predicted result is the length of the string is shorter than the threshold and a second flow when the predicted result is the length of the string is not shorter than the threshold; a read stage to read the operand; and execution circuitry to begin executing the generated micro-operation flow on the operand, read the length of string, and continue executing the generated micro-operation flow if the predicted result of the length of the string being shorter than the threshold was correct based on the length of the string, and, otherwise, to flush the pipeline, update the predicted result based on the length of the string, and switch from the generated micro-operation flow to the other of the first and second flows. ### Claim 2 (depends on 1) The processor of claim 1, wherein the opcode indicates either a store or a move of the string. ### Claim 3 (depends on 1) The processor of claim 1, wherein the threshold is set by a software-programmable model-specific register. ### Claim 4 (depends on 1) The processor of claim 1, wherein the length of the string is to be determined by a read of a register during execution of the generated micro-operation flow. ### Claim 5 (depends on 1) The processor of claim 1, wherein the instruction further specifies a destination. ### Claim 6 (depends on 1) The processor of claim 1, wherein the read of the length of the string comprises testing a value of one or more architectural registers. ### Claim 7 (depends on 1) The processor of claim 1, wherein the BPU includes a branch history memory to store results of past conditional branches, the branch history memory to inform the predicted result. ### Claim 8 (depends on 1) The processor of claim 1, wherein the decode stage comprises a micro-sequencer to select one or more micro-operations from a microcode read-only memory (ROM) to form each of the first and second flows. ### Claim 9 A method performed by a processor having a branch prediction unit (BPU) and a pipeline, the method comprising: fetching an instruction specifying an opcode, an operand that is a string, and a length of the string, wherein the BPU is to generate a hint reflecting a predicted result of whether the length of the string is shorter than a threshold; generating a micro-operation flow comprising a first flow when the predicted result is the length of the string is shorter than the threshold and a second flow when the predicted result is the length of the string is not shorter than the threshold; beginning to execute the generated micro-operation flow; subsequently, reading the length of the string; and continuing to execute the generated micro-operation flow if the predicted result of the length of the string being shorter than the threshold was correct based on the length of the string, and, otherwise, flushing the pipeline, updating the predicted result based on the length of the string, and switching from the generated micro-operation flow to the other of the first and second flows. ### Claim 10 (depends on 9) The method of claim 9, wherein the opcode indicates either a store or a move of the string. ### Claim 11 (depends on 9) The method of claim 9, wherein the threshold is set by a software-programmable model-specific register. ### Claim 12 (depends on 9) The method of claim 9, wherein the reading the length of the string comprises reading a register during execution of the generated micro-operation flow. ### Claim 13 (depends on 9) The method of claim 9, wherein the reading the length of the string comprises testing a value of one or more architectural registers. ### Claim 14 (depends on 9) The method of claim 9, wherein the BPU includes a branch history memory to store results of past conditional branches, the branch history memory to inform the predicted result. ### Claim 15 (depends on 9) The method of claim 9, wherein the generating the micro-operation flow is performed by decode circuitry comprising a micro-sequencer to select one or more micro-operations from a microcode read-only memory (ROM) to form each of the first and second micro-operation flows. ### Claim 16 A non-transitory machine-readable medium containing code to which a processor comprising a branch prediction unit (BPU) and a pipeline is to respond by: fetching, in a fetch stage, an instruction specifying an opcode, an operand that is a string, and a length of the string, wherein the BPU is to generate a hint reflecting a predicted result of whether the length of the string is shorter than a threshold; generating a micro-operation flow comprising a first flow when the predicted result is the length of the string is shorter than the threshold and a second flow when the predicted result is the length of the string is not shorter than the threshold; beginning to execute the generated micro-operation flow; subsequently, reading the length of the string; and continuing to execute the generated micro-operation flow if the predicted result of the length of the string being shorter than the threshold was correct based on the length of the string, and, otherwise, flushing the pipeline, updating the predicted result based on the length of the string, and switching from the generated micro-operation flow to the other of the first and second flows. ### Claim 17 (depends on 16) The non-transitory machine-readable medium of claim 16, wherein the opcode indicates either a store or a move of the string. ### Claim 18 (depends on 16) The non-transitory machine-readable medium of claim 16, wherein the threshold is set by a software-programmable model-specific register. ### Claim 19 (depends on 16) The non-transitory machine-readable medium of claim 16, wherein the reading the length of the string comprises reading a register during execution of the generated micro-operation flow. ### Claim 20 (depends on 16) The non-transitory machine-readable medium of claim 16, wherein the reading the length of the string comprises testing a value of one or more architectural registers.