# US 11,029,893 B2 · Storage device including nonvolatile memory device and controller, controller and operating method of nonvolatile memory device

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- Number: US 11,029,893 B2
- Document ID: US11029893B2
- Status: Granted
- Kind: B2
- Application number: 15/970,237
- Filed: 2018-05-03
- Published: 2019-03-14
- Granted: 2021-06-08
- Earliest claimed: 2017-09-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jesuk Yeon; Seontaek Kim; Young-Ho Park; Eun Ju Choi; Yonghwa Lee
- Web page: https://patentgrep.com/patent/US11029893B2

## CPC

- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0611: {in relation to response time}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 3/167: {Audio in a user interface, e.g. using voice commands for navigating, audio feedback}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/10: Address translation
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7207: management of metadata or control data
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.

## Claims

### Claim 1

An operating method of a storage device which includes a nonvolatile memory device and a controller, the controller including a command queue and a sub-queue, the method comprising:
receiving, at the controller, a plurality of read commands and a write command from an external device, the write command being associated with write data;
enqueueing the plurality of read commands and the write command in the command queue;
fetching a command from the command queue;
in response to the fetched command being a read command among the plurality of read commands, accessing the nonvolatile memory device based on the fetched read command;
in response to the fetched command being the write command, slicing, at the controller, the write command to generate a plurality of sub-commands;
slicing, at the controller, the write data to generate a plurality of sub-data elements;
enqueueing the plurality of sub-commands in the sub-queue;
in response to the sub-queue including at least one sub-command,
alternately performing fetching of the command from the command queue and fetching of a sub-command from the sub-queue; and
in response to fetching the sub-command, sending the fetched sub-command and a sub-data element corresponding to the sub-command among the plurality of sub-data elements.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of read commands and the write command have the same priority.

### Claim 3

A storage device comprising:
a nonvolatile memory device; and
a controller including a command queue and a sub-queue,
wherein the controller is configured to,
receive first read commands and a first write command, the first write command being associated with first write data,
enqueue the first read commands and the first write command in the command queue,
fetch a command from the command queue,
in response to the fetched command being a read command among the first read commands, sending the fetched read command to the nonvolatile memory device,
in response to the fetched command being the first write command, slice the first write command to generate a plurality of sub-commands,
slice the first write data corresponding to the write command to generate a plurality of sub-data elements,
enqueue the plurality of sub-commands in the sub-queue,
in response to the sub-queue including at least one sub-command, alternately performing fetching of the command from the command queue and fetching of a sub-command from the sub-queue, and
in response to fetching the sub-command, sending the fetched sub-command and a sub-data element corresponding to the sub-command among the plurality of sub-data elements.

### Claim 4 (depends on 3)

The storage device of claim 3, wherein the controller is further configured to,
divide an address range of the fetched command or the fetched sub-command into divided address ranges depending on a translation unit and to translate the divided address ranges into device address ranges, and
transmit each of the device address ranges to the nonvolatile memory device together with a device access command corresponding to the fetched command.

### Claim 5 (depends on 3)

The storage device of claim 3, wherein,
the controller is further configured such that,
the controller increments a count value in response to sending the fetched read command to the nonvolatile memory device while the count value is under a write threshold, and
the controller performs fetching of the sub-command in response to the count value reaching the write threshold.

### Claim 6 (depends on 5)

The storage device of claim 5, wherein the controller is configured to,
reset the count value after sending the fetched sub-command.

### Claim 7 (depends on 5)

The storage device of claim 5, wherein, in response to the first write command being received when a pending write command is absent at the controller, the controller is further configured to fetch the sub-command and the sub-data element.

### Claim 8 (depends on 5)

The storage device of claim 5, wherein the controller is further configured to decrease the write threshold in response to a number of write commands pending in the controller increasing, a size of write data pending in the controller increasing, a delay of the pending write commands increasing, or a busy ratio of the controller increasing.

### Claim 9 (depends on 5)

The storage device of claim 5, wherein the controller is further configured to increase the write threshold in response to a ratio of write resources under use by the controller increasing, or a ratio of read commands to write commands received by the controller increasing.

### Claim 10 (depends on 3)

The storage device of claim 3, wherein the controller is further configured to,
generate a plurality of device commands by slicing each of the fetched one read command and the fetched sub-command by a translation unit within an associated address range, and
transmit the plurality of device commands, sequentially.

### Claim 11 (depends on 3)

The storage device of claim 3, further comprising:
a random access memory,
wherein the first write data is stored in the random access memory and the random access memory is configured to transmit the first write data to the nonvolatile memory device through the controller by a unit of the fetched sub-data element.

### Claim 12 (depends on 3)

The storage device of claim 3, wherein the controller is further configured to complete a write operation associated with the fetched first write command and the first write data by transmitting, to the nonvolatile memory device, an entirety of the fetched first write command and the first write data in the form of the plurality of sub-commands and the plurality of sub-data elements.

### Claim 13 (depends on 3)

The storage device of claim 3, wherein,
the controller is further configured to receive,
second read commands, and
a second write command that is associated with second write data, and
in response to the fetched command being the second write command and a size of the second write data being under a size threshold, the controller is further configured to transmit the second write command and the second write data to the nonvolatile memory device, without slicing the second write command.

### Claim 14 (depends on 13)

The storage device of claim 13, wherein,
in response to the fetched command being the second write command and a number of free entities of the sub-queue being under a lower threshold, the controller is further configured to transmit the second write command and the second write data to the nonvolatile memory device without slicing the second write command, regardless of the size threshold.

### Claim 15 (depends on 14)

The storage device of claim 14, wherein the controller is further configured such that the controller decreases the size threshold as the number of free entities of the sub-queue increases.

### Claim 16 (depends on 3)

The storage device of claim 3, wherein,
the controller is further configured to receive,
second read commands, and
a second write command that is associated with second write data, and in response to the fetched command being the second write command and a number of write commands pending in the controller exceeding an upper threshold, the controller transmits the second write command to the nonvolatile memory device without slicing the second write command.