# US 11,029,889 B1 · Soft bit read mode selection for non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,889 B1 - Document ID: US11029889B1 - Status: Granted - Kind: B1 - Application number: 16/723,192 - Filed: 2019-12-20 - Published: 2021-06-24 - Granted: 2021-06-08 - Earliest claimed: 2019-12-20 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Eran Sharon; Alex Bazarsky; Idan Alrod - Web page: https://patentgrep.com/patent/US11029889B1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2013/0045: {Read using current through the cell} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times. ## Claims ### Claim 1 An apparatus, comprising: an array of non-volatile memory cells; and a controller configured to: select a read mode from a plurality of read modes for reading data from a region of the array, the plurality of read modes comprising at least a time-based soft bit read mode; apply a set of bias conditions to cells of the region such that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region; and in response to selecting the time-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at multiple integration times. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein: the plurality of read modes further comprises a hard bit read mode and a bias-based soft bit read mode; and the controller is further configured to: in response to selecting the hard bit read mode, read hard bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at a single integration time; and in response to selecting the bias-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, applying one or more additional sets of bias conditions, and sensing the capacitor voltages resulting from the one or more additional sets of bias conditions. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the time-based soft bit read mode is a default read mode for the controller. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is configured to sense capacitor voltages at two integration times in the time-based soft bit read mode, and to sense capacitor voltages at three integration times in a second time-based soft bit read mode. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the controller is configured to select the read mode based on information included in a read command received by the controller. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the multiple integration times comprise a set of times selected by the controller based on information included in a read command received by the controller. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller is configured to select the read mode based on metadata recorded at write time for the region. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the controller is configured to select the read mode based on a comparison of the current time and temperature to time and temperature metadata recorded at write time for the region. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the controller is configured to select the read mode based on error correction information for the region. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the controller is configured to select the read mode based on error correction information for a second region of the array, and on metadata recorded at write time for the region and the second region. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the multiple integration times comprise a set of times selected by the controller based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the array, and metadata recorded at write time for the second region. ### Claim 12 A method, comprising: determining whether to use a time-based soft bit read mode for reading data from a region of non-volatile memory; applying a set of bias voltages to cells of the region such that states of the cells affect analog voltages at sense amplifiers associated with the cells; and in response to determining to use the time-based soft bit read mode, reading hard bits and soft bits for the region by converting the analog voltages affected by the applied bias voltages to digital sense amplifier results, at multiple integration times. ### Claim 13 (depends on 12) The method of claim 12, further comprising selecting whether to convert the analog voltages to digital sense amplifier results at two integration times or at three integration times. ### Claim 14 (depends on 12) The method of claim 12, further comprising determining the multiple integration times based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the non-volatile memory, and metadata recorded at write time for the second region. ### Claim 15 (depends on 12) The method of claim 12, wherein determining whether to use a time-based soft bit read mode comprises comparing a current time and temperature to time and temperature metadata recorded at write time for the region. ### Claim 16 (depends on 12) The method of claim 12, wherein determining whether to use a time-based soft bit read mode is based on error correction information for the region. ### Claim 17 (depends on 12) The method of claim 12, wherein determining whether to use a time-based soft bit read mode is based on error correction information for a second region of the non-volatile memory, and on metadata recorded at write time for the region and the second region. ### Claim 18 An apparatus, comprising: means for selecting a read mode from a plurality of read modes for reading data from a region of non-volatile memory, the plurality of read modes comprising at least a time-based soft bit read mode; means for producing analog voltages based on data stored by cells of the region; and means for digitizing the analog voltages at a number of integration times based on the selected read mode. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the means for selecting a read mode comprises comprising means for comparing a current time and temperature to time and temperature metadata recorded at write time for the region. ### Claim 20 (depends on 18) The apparatus of claim 18, further comprising means for determining the integration times based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the non-volatile memory, and metadata recorded at write time for the second region.