# US 11,029,885 B2 · Memory controller for controlling multiple types of flash memories, and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,885 B2 - Document ID: US11029885B2 - Status: Granted - Kind: B2 - Application number: 16/576,267 - Filed: 2019-09-19 - Published: 2020-05-21 - Granted: 2021-06-08 - Earliest claimed: 2018-11-15 - Assignees: TDK Corporation - Applicants: TDK Corporation - Inventors: Naoki Mukaida; Kenichi Takubo - Web page: https://patentgrep.com/patent/US11029885B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 8/654: using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories - G06F 3/0605: {by facilitating the interaction with a user or administrator} - G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 8/71: Version control (security arrangements therefor G06F21/57); Configuration management - G06F 9/5016: {the resource being the memory} - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G06F 12/0882: Page mode - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F 2212/1024: Latency reduction - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/1056: Simplification - G06F 2212/7206: Reconfiguration of flash memory system - G06F 2212/7207: management of metadata or control data - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory controller controls access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller allocates a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, writes the management information necessary for accessing the flash memory to the prescribed physical block, and operates to search for the prescribed physical block when second firmware is read from the flash memory. The writing information, including the management information, is written to the prescribed physical block in a same format regardless of a type of flash memory. Information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block. ## Claims ### Claim 1 A memory controller for controlling access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system, the memory controller comprising: a read-only memory (ROM) to which first firmware is written; a random access memory (RAM) to which second firmware read from the flash memory is written; and a buffer configured to hold transmission and reception data to and from the host system or the flash memory, wherein the memory controller is configured to operate based on the first firmware or the second firmware, wherein the memory controller is configured to allocate a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, write the management information necessary for accessing the flash memory to the prescribed physical block, and operate to search in an order for the prescribed physical block when the second firmware is read from the flash memory, wherein writing information, the writing information including the management information, is written to the prescribed physical block in a same format regardless of a type of flash memory, wherein information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block, wherein the memory controller is configured to write identification information for identifying the prescribed physical block to the prescribed physical block, wherein the memory controller is configured to operate to search for the prescribed physical block based on the identification information at the time of activation, wherein a condition for determining that the prescribed physical block has been found includes a condition that the identification information for identifying the prescribed physical block is included in the sequentially read information, and wherein the identification information is also written to the prescribed physical block in the same format regardless of a type of flash memory. ### Claim 2 (depends on 1) The memory controller according to claim 1, wherein the memory controller is configured to determine that the prescribed physical block is found when error correction is performed by means of an error correction code included in the read information. ### Claim 3 (depends on 1) The memory controller according to claim 1, wherein the prescribed page interval is an interval of the number of pages corresponding to a common divisor of the number of pages included in one block for a plurality of types of flash memories that are used. ### Claim 4 (depends on 2) The memory controller according to claim 2, wherein the prescribed page interval is an interval of the number of pages corresponding to a common divisor of the number of pages included in one block for a plurality of types of flash memories that are used. ### Claim 5 A memory system including a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, and a memory controller configured to control access to the flash memory based on a command assigned from a host system, wherein the memory controller includes: a read-only memory (ROM) to which first firmware is written; a random access memory (RAM) to which second firmware read from the flash memory is written; and a buffer configured to hold transmission and reception data to and from the host system or the flash memory, wherein the memory controller is configured to operate based on the first firmware or the second firmware, wherein the memory controller is configured to allocate a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, write the management information necessary for accessing the flash memory to the prescribed physical block, and operate to search in an order for the prescribed physical block when the second firmware is read from the flash memory, wherein writing information, the writing information including the management information, is written to the prescribed physical block in a same format regardless of type of flash memory, wherein information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block, wherein the memory controller is configured to write identification information for identifying the prescribed physical block to the prescribed physical block, wherein the memory controller is configured to operate to search for the prescribed physical block based on the identification information at the time of activation, wherein a condition for determining that the prescribed physical block has been found includes a condition that the identification information for identifying the prescribed physical block is included in the sequentially read information, and wherein the identification information is also written to the prescribed physical block in the same format regardless of a type of flash memory. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein the prescribed page interval is an interval of the number of pages corresponding to a common divisor of the number of pages included in one block for a plurality of types of flash memories that are used.