# US 11,029,883 B2 · Reduce system active power based on memory usage patterns

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- Number: US 11,029,883 B2
- Document ID: US11029883B2
- Status: Granted
- Kind: B2
- Application number: 16/484,066
- Filed: 2018-12-28
- Published: 2020-07-23
- Granted: 2021-06-08
- Earliest claimed: 2018-12-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Xinghui Duan; Eric Kwok Fung Yuen; Zhi Ping Yu; Guanzhong Wang
- Web page: https://patentgrep.com/patent/US11029883B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 1/3225: of memory devices
- G06F 1/324: by lowering clock frequency
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 13/1668: {Details of memory controller}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.

## Claims

### Claim 1

A memory device comprising:
a memory array including memory cells;
a communication interface configured for communicating with a host; and
a memory control unit operatively coupled to the memory array and the communication interface, and including a queue and a bus configured to transfer data between the memory control unit and memory array;
wherein the memory control unit includes error correction code (ECC) circuitry, and the memory control unit is configured to:
store requests to access the memory in the queue;
determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array;
reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array; and
reduce a frequency of a clock signal of the ECC circuitry when the queued memory access requests are to random addresses of the memory array.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory control unit includes a processor configured to process the requests to access the memory, and the memory control unit is configured to reduce a frequency of a clock signal of the processor when the queued memory access requests are to sequential addresses of the memory array.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the memory control unit includes a flash controller to transfer data using the bus and the memory control unit is configured to reduce a frequency of a clock signal of the flash controller when the queued memory access requests are to random addresses of the memory array.

### Claim 4

The memory device of 1,
wherein the memory control unit is configured to:
reduce a frequency of a clock signal of the processor and maintain a frequency of a clock signal of the flash controller when the queued memory access requests are to sequential addresses of the memory array, and
maintain a frequency of a clock signal of the processor and reduce a frequency of a clock signal of the flash controller when the queued memory access requests are to random addresses of the memory array.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the queued memory access requests are memory write requests.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the queued memory access requests are memory read requests.

### Claim 7

A method of operating a memory device, the method comprising:
queueing requests to access the memory using a command queue of the memory device;
determining whether the queued access requests are to sequential addresses of a memory array or to random addresses of the memory array;
reducing an operating rate of one or more first components of the memory device when the queued access requests are to sequential addresses of the memory array, wherein reducing an operating rate of the one or more first components includes reducing a frequency of a clock signal of the one or more first components and maintaining a frequency of a clock signal of the one or more second components when the queued access requests are to sequential addresses of the memory array; and
reducing an operating rate of one or more second components of the memory device when the queued access requests are to random addresses of the memory array, wherein reducing an operating rate of the one or more second components includes reducing a frequency of a clock signal of the one or more second components and maintaining a frequency of a clock signal of the one or more first components when the queued access requests are to random addresses of the memory array.

### Claim 8 (depends on 7)

The method of claim 7, wherein the requests to access the memory are memory write requests.

### Claim 9 (depends on 7)

The method of claim 7, wherein the requests to access the memory are memory read requests.

### Claim 10 (depends on 7)

The method of claim 7, wherein determining whether queued access requests are to sequential addresses or random addresses includes determining whether queued access requests are to sequential addresses or random addresses using a command word included in the access requests.

### Claim 11 (depends on 7)

The method of claim 7, wherein determining whether queued access requests are to sequential addresses or random addresses includes determining whether queued access requests are to sequential addresses or random addresses using a command chunk size of the access requests.

### Claim 12 (depends on 7)

The method of claim 7, wherein the one or more first components include a processor of the memory device configured to process the requests to access the memory.

### Claim 13 (depends on 7)

The method of claim 7, wherein the one or more second components include one or more of error correction code (ECC) circuitry of the memory device and a flash controller of the memory device, the flash controller configured to transfer memory write data and memory read data using a bus.

### Claim 14 (depends on 7)

The method of claim 7, including:
maintaining the operating rate of the one or more second components of the memory device when the queued access requests are to sequential addresses of the memory array; and
maintaining the operating rate of the one or more first components of the memory device when the queued access requests are to random addresses of the memory array.

### Claim 15

A non-transitory computer readable storage medium comprising instructions configured to cause a memory control unit of a memory device to:
queue requests to access the memory using a queue of the memory device;
determine whether the queued access requests are to sequential addresses of a memory array or to random addresses of the memory array;
reduce an operating rate of one or more first components of the memory device when the queued access requests are to sequential addresses of the memory array; and
reduce an operating rate of one or more of error correction code (ECC) circuitry and a flash controller of the memory control unit when the queued access requests are to random addresses of the memory array.

### Claim 16 (depends on 15)

The non-transitory computer readable storage medium of claim 15, including instructions configured to cause the memory control unit to
reduce a frequency of a clock signal of the one or more first components and maintain a frequency of a clock signal of the one or more second components when the queued access requests are to sequential addresses of the memory array; and
reduce a frequency of a clock signal of the one or more second components and maintain a frequency of a clock signal of the one or more first components when the queued access requests are to random addresses of the memory array.

### Claim 17 (depends on 15)

The non-transitory computer readable storage medium of claim 15, including instructions configured to cause the memory control unit to reduce an operating rate of a processor of the memory control unit when the queued access requests are to sequential addresses of the memory array.

### Claim 18

A memory device comprising:
a memory array including memory cells;
a communication interface configured for communicating with a host; and
a memory control unit operatively coupled to the memory array and the communication interface, and including a queue, the memory control unit configured to:
store requests to access the memory in the queue;
determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array using one or more of a command chunk size or an address range of the memory access requests;
reduce an operating rate of a first component of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, wherein the first component is a processor, and the memory control unit is configured to reduce a frequency of a clock signal of the processor when the queued memory access requests are to sequential addresses of the memory array; and
reduce an operating rate of a second component of the memory control unit when the queued memory access requests are to random addresses of the memory array, wherein the second component includes error correction code (ECC) circuitry, and the memory control unit is configured to reduce a frequency of a clock signal of the ECC circuitry when the queued memory access requests are to random addresses of the memory array.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the memory device includes multiple memory arrays that include memory cells, and the memory control unit includes a queue for each memory array.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the memory cells of the memory array are a subset of the total memory cells of a memory die.

### Claim 21 (depends on 18)

The memory device of claim 18, wherein the memory array is included in a memory plane of a memory die.