# US 11,029,870 B2 · Technologies for dividing work across accelerator devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,870 B2 - Document ID: US11029870B2 - Status: Granted - Kind: B2 - Application number: 15/721,829 - Filed: 2017-09-30 - Published: 2018-05-31 - Granted: 2021-06-08 - Earliest claimed: 2016-11-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Susanne M. Balle; Francesc Guim Bernat; Slawomir Putyrski; Joe Grecco; Henry Mitchel; Evan Custodio; Rahul Khanna; Sujoy Sen - Web page: https://patentgrep.com/patent/US11029870B2 ## CPC - G06F 9/5005: {to service a request} - H04L 41/0895: Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements - G06F 8/65: Updates (security arrangements therefor G06F21/57) - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/5044: {considering hardware capabilities} - G06F 9/505: {considering the load} - G06F 9/5083: {Techniques for rebalancing the load in a distributed system} - G06F 11/0709: {in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems} - G06F 11/3006: {where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50)} - G06F 11/3079: {the data filtering being achieved by reporting only the changes of the monitored data} - G06F 11/3409: {for performance assessment} - G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 15/161: {Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning (casings, cabinets, racks or drawers for data centers H05K5/00)} - G06F 21/44: Program or device authentication - G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities - G06F 21/70: Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer - G06F 21/73: by creating or determining hardware identification, e.g. serial numbers - H03K 19/1731: {Optimisation thereof} - H04L 41/0816: the condition being an adaptation, e.g. in response to network events - H04L 41/0853: by actively collecting configuration information or by backing up configuration information - H04L 41/12: Discovery or management of network topologies - H04L 41/40: using virtualisation of network functions or resources, e.g. SDN or NFV entities - H04L 47/83: based on usage prediction - H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) - H05K 7/1492: {having electrical distribution arrangements, e.g. power supply or data communications} - H04L 47/78: Architectures of resource allocation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job. ## Claims ### Claim 1 A compute device comprising: one or more accelerator devices; and a compute engine to: determine a configuration of at least one accelerator device of the compute device, wherein the configuration is indicative of parallel execution capabilities of the at least one accelerator device, and wherein to determine the configuration includes to determine for the at least one accelerator device whether the at least one accelerator device is capable of accessing a shared data set and whether the at least one accelerator device is capable of accessing a shared memory; receive, from a requester device, a job to be accelerated; divide the job into multiple tasks for a parallel execution of the multiple tasks among the one or more accelerator devices as a function of a job analysis of the job and the configuration of the at least one accelerator device indicative of whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; schedule the multiple tasks to the one or more accelerator devices based on the job analysis; execute the multiple tasks on the one or more accelerator devices for parallel execution of the multiple tasks based on whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; and combine task outputs from the one or more accelerator devices that executed the multiple tasks to obtain an output of the job. ### Claim 2 (depends on 1) The compute device of claim 1, wherein the compute engine includes a micro-orchestrator logic unit. ### Claim 3 (depends on 2) The compute device of claim 2, wherein to determine the configuration of the at least one accelerator device comprises to determine, by the micro-orchestrator logic unit of the compute device, the configuration of the at least one accelerator device. ### Claim 4 (depends on 1) The compute device of claim 1, wherein the compute engine is further to determine an availability of one or more of the accelerator devices. ### Claim 5 (depends on 4) The compute device of claim 4, wherein to determine the availability of one or more of the accelerator devices comprises to determine one or more available kernels of each accelerator device. ### Claim 6 (depends on 1) The compute device of claim 1, wherein to schedule the multiple tasks to the one or more accelerator devices comprises to schedule parallel execution of the tasks. ### Claim 7 (depends on 1) The compute device of claim 1, wherein to schedule the multiple tasks to the one or more accelerator devices comprises to confirm that the one or more accelerator devices are available to simultaneously execute multiple tasks that share data. ### Claim 8 (depends on 1) The compute device of claim 1, wherein to execute the multiple tasks comprises to concurrently execute two or more of the tasks on two or more of the accelerator devices of the compute device with a high speed serial interface (HSSI). ### Claim 9 (depends on 1) The compute device of claim 1, wherein the compute engine is further to: determine whether an authorization is required from an orchestrator to execute the tasks on the compute device; transmit, in response to a determination that the authorization is required, the job analysis to the orchestrator; receive an authorization from the orchestrator; and receive the tasks to be accelerated. ### Claim 10 (depends on 9) The compute device of claim 9, wherein the compute device comprises a first compute device, and wherein to execute the multiple tasks comprises to: determine one or more accelerator devices of a second compute device that is remote to the first compute device to concurrently execute the multiple tasks that share data; and execute one or more of the tasks on the one or more accelerator devices of the first compute device as one or more other tasks of the job are concurrently executed with one or more accelerator devices of the second compute device using a shared virtual memory. ### Claim 11 (depends on 10) The compute device of claim 10, wherein to determine the one or more accelerator devices of the second compute device comprises to receive information regarding one or more accelerator devices of the second compute device from an orchestrator server. ### Claim 12 (depends on 9) The compute device of claim 9, wherein to execute the tasks comprises to execute the tasks simultaneously on the one or more accelerator devices of the compute device with a high speed serial interface (HSSI). ### Claim 13 One or more machine-readable storage media comprising a plurality of instructions stored thereon that, when executed by at least one compute device cause the at least one compute device to: determine a configuration of at least one accelerator device of the compute device, wherein the configuration is indicative of parallel execution capabilities of at least one accelerator device, and wherein to determine the configuration includes to determine, for at least one accelerator device, whether the at least one accelerator device is capable of accessing a shared data set and whether the at least one accelerator device is capable of accessing a shared memory; receive, from a requester device, a job to be accelerated; divide the job into multiple tasks for a parallel execution of the multiple tasks among the one or more accelerator devices as a function of a job analysis of the job and the configuration of at least one accelerator device indicative of whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; schedule the multiple tasks to the one or more accelerator devices based on the job analysis; cause execution of the multiple tasks on the one or more accelerator devices for the parallel execution of the multiple tasks based on whether the at least one accelerator device is capable of accessing the shared data set and whether the one or more accelerator device is capable of accessing the shared memory; and combine task outputs from the one or more accelerator devices that executed the multiple tasks to obtain an output of the job. ### Claim 14 (depends on 13) The one or more machine-readable storage media of claim 13, wherein to determine the configuration of at least one accelerator device comprises to determine, by a micro-orchestrator logic unit of the compute device, the configuration of the at least one accelerator device. ### Claim 15 (depends on 13) The one or more machine-readable storage media of claim 13, further comprising a plurality of instructions stored thereon that, in response to being executed, cause the compute device to determine an availability of one or more of the accelerator devices, and the at least one of the accelerator devices is not a general purpose processor. ### Claim 16 (depends on 15) The one or more machine-readable storage media of claim 15, wherein to determine the availability of one or more of the accelerator devices comprises to determine one or more available kernels of the at least one accelerator device. ### Claim 17 (depends on 13) The one or more machine-readable storage media of claim 13, wherein to schedule the multiple tasks to the one or more accelerator devices comprises to schedule parallel execution of the tasks. ### Claim 18 (depends on 13) The one or more machine-readable storage media of claim 13, wherein to schedule the multiple tasks to the one or more accelerator devices comprises to confirm that the one or more accelerator devices are available to simultaneously execute multiple tasks that share data. ### Claim 19 (depends on 13) The one or more machine-readable storage media of claim 13, wherein execution of the multiple tasks comprises concurrently execute two or more of the tasks on two or more of the accelerator devices of the compute device with a high speed serial interface (HSSI). ### Claim 20 (depends on 13) The one or more machine-readable storage media of claim 13, further comprising a plurality of instructions stored thereon that, in response to being executed, cause the compute device to: determine whether an authorization is required from an orchestrator to execute the tasks on the compute device; transmit, in response to a determination that the authorization is required, the job analysis to the orchestrator; receive an authorization from the orchestrator; and receive the tasks to be accelerated. ### Claim 21 (depends on 20) The one or more machine-readable storage media of claim 20, wherein the compute device comprises a first compute device, and wherein to execute the tasks comprises to: determine one or more accelerator devices of a second compute device that is remote to the first compute device to concurrently execute the tasks that share data; and execute one or more of the tasks on the one or more accelerator devices of the first compute device as one or more other tasks of the job are concurrently executed with one or more accelerator devices of the second compute device using a shared virtual memory. ### Claim 22 (depends on 21) The one or more machine-readable storage media of claim 21, wherein to determine one or more accelerator devices of the second compute device comprises to receive information regarding one or more accelerator devices of the second compute device from a server. ### Claim 23 (depends on 20) The one or more machine-readable storage media of claim 20, wherein to execute the tasks comprises to execute the tasks simultaneously on the one or more accelerator devices of the compute device with a high speed serial interface (HSSI). ### Claim 24 A compute device comprising: circuitry for determining a configuration of at least one of one or more accelerator devices of the compute device, wherein the configuration is indicative of parallel execution capabilities of at least one accelerator device, and wherein determining the configuration includes determining for the at least one accelerator device whether the accelerator device is capable of accessing a shared data set and whether the at least one accelerator device is capable of accessing a shared memory; circuitry for receiving, from a requester device remote from the compute device, a job to be accelerated; means for dividing the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of the at least one accelerator device indicative of whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; means for scheduling the multiple tasks to the one or more accelerator devices based on the job analysis; circuitry for executing the multiple tasks on the one or more accelerator devices for the parallelization of the multiple tasks based on whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; and means for combining task outputs from the at least one accelerator devices that executed the multiple tasks to obtain an output of the job. ### Claim 25 A method comprising: determining, by a compute device, a configuration of at least one of one or more accelerator devices of the compute device, wherein the configuration is indicative of parallel execution capabilities of at least one accelerator device, and wherein determining the configuration includes determining for at least one accelerator device whether the accelerator device is capable of accessing a shared data set and whether the accelerator device is capable of accessing a shared memory; receiving, from a requester device and by the compute device, a job to be accelerated; dividing, by the compute device, the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of at least one accelerator device indicative of whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; scheduling, by the compute device, the multiple tasks to the one or more accelerator devices based on the job analysis; causing execution, by the compute device, of the multiple tasks on the one or more accelerator devices for the parallelization of the multiple tasks based on whether the at least one accelerator device is capable of accessing the shared data set and whether the at least one accelerator device is capable of accessing the shared memory; and combining, by the compute device, task outputs from the one or more accelerator devices that executed the tasks to obtain an output of the job. ### Claim 26 (depends on 25) The method of claim 25, wherein determining the configuration of at least one accelerator device comprises determining, by a micro-orchestrator logic unit of the compute device, the configuration of at least one accelerator device. ### Claim 27 (depends on 25) The method of claim 25, further comprising: determining, by the compute device, whether an authorization is required from an orchestrator to execute the tasks on the compute device; transmitting, by the compute device and in response to a determination that the authorization is required, the job analysis to the orchestrator; receiving, by the compute device, an authorization from the orchestrator; and receiving, by the compute device, the tasks to be accelerated. ### Claim 28 (depends on 27) The method of claim 27, wherein the compute device comprises a first compute device, and wherein executing the tasks comprises: determining, by the first compute device, one or more accelerator devices of a second compute device that is remote to the first compute device to concurrently execute the multiple tasks that share data; and executing one or more of the tasks on the one or more accelerator devices of the first compute device as one or more other tasks of the job are concurrently executed with one or more accelerator devices of the second compute device using a shared virtual memory.