# US 11,029,861 B2 · Sense flags in a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,861 B2 - Document ID: US11029861B2 - Status: Granted - Kind: B2 - Application number: 16/543,743 - Filed: 2019-08-19 - Published: 2019-12-05 - Granted: 2021-06-08 - Earliest claimed: 2010-11-09 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Shafqat Ahmed; Khaled Hasnat; Pranav Kalavade; Krishna Parat; Aaron Yip; Mark A. Helm; Andrew Bicksler - Web page: https://patentgrep.com/patent/US11029861B2 ## CPC - G06F 3/0625: {Power saving in storage systems} - G06F 3/061: {Improving I/O performance} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0665: {at area level, e.g. provisioning of virtual or logical volumes} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 3/0689: {Disk arrays, e.g. RAID, JBOD} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F 2212/2022: Flash memory - G06F 2212/224: Disk storage - G06F 2212/461: Sector or disk block - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed. ## Claims ### Claim 1 A memory device, comprising: an array of memory cells comprising a plurality of pages of memory cells; and control circuitry for access of the array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: reading a first page of memory cells, of the plurality of pages of memory cells, and flag data from a set of flag cells wherein the flag data indicates whether a second page of memory cells, of the plurality of pages of memory cells, adjacent to the first page is programmed; and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage. ### Claim 2 (depends on 1) The memory device of claim 1 wherein, in the method that the control circuitry is configured to cause the memory to perform, reading the first page of memory cells and the flag data is performed with one read operation. ### Claim 3 (depends on 1) The memory device of claim 1 wherein the first page of memory cells is an even page, the second page is an odd page, and the flag data indicates whether the odd page is programmed. ### Claim 4 A memory device, comprising: a first array of memory cells; a second array of memory cells; and control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: performing a sense operation on memory cells of the first array of memory cells coupled to first data lines of the first array of memory cells, and on memory cells of the second array of memory cells coupled to data lines of the second array of memory cells, without performing the sense operation on memory cells of the first array of memory cells coupled to second data lines of the first array of memory cells; and determining a program indication of the memory cells coupled to the second data lines of the first array of memory cells from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells. ### Claim 5 (depends on 4) The memory device of claim 4, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the first array of memory cells when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are not programmed. ### Claim 6 (depends on 4) The memory device of claim 4, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: determining states of the memory cells coupled to the first data lines of the first array of memory cells without adjustment of read gate voltages when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are programmed. ### Claim 7 (depends on 4) The memory device of claim 4, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: performing a sense operation on a lower page of the memory cells coupled to the first data lines responsive to the program indication. ### Claim 8 (depends on 4) The memory device of claim 4, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the first array of memory cells when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are programmed. ### Claim 9 (depends on 4) The memory device of claim 4, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: determining states of the memory cells coupled to the first data lines of the first array of memory cells without adjustment of read gate voltage when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are not programmed. ### Claim 10 A memory device, comprising: a first array of memory cells; a second array of memory cells; and control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: programming memory cells coupled to first data lines in the first array of memory cells without programming memory cells coupled to second data lines in the first array of memory cells and without programming memory cells coupled to data lines in the second array of memory cells; and programming the memory cells coupled to the second data lines in the first array of memory cells while programming the memory cells coupled to the data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed. ### Claim 11 (depends on 10) The memory device of claim 10, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: loading user data into a dynamic data cache of the memory device coupled to the first data lines prior to programming the memory cells coupled to the first data lines. ### Claim 12 (depends on 11) The memory device of claim 11, wherein, in the method that the control circuitry is configured to cause the memory to perform, programming the memory cells coupled to the first data lines in the first array of memory cells comprises programming the memory cells coupled to the first data lines in the first array of memory cells with the user data loaded into the dynamic data cache. ### Claim 13 (depends on 10) The memory device of claim 10, wherein the flag data comprises a plurality of bytes of data. ### Claim 14 (depends on 10) The memory device of claim 10, wherein a first data line of the first data lines in the first array of memory cells and a second data line of the second data lines in the first array of memory cells are adjacent first and second data lines. ### Claim 15 (depends on 14) The memory device of claim 14, wherein, in the method that the control circuitry is configured to cause the memory to perform, a read gate voltage of the memory cell coupled to the first data line of the adjacent first and second data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed. ### Claim 16 A memory device, comprising: a first array of memory cells; a second array of memory cells; a third array of memory cells; and control circuitry for access of the first array of memory cells, the second array of memory cells and the third array of memory cells, Wherein the control circuitry is configured to cause the memory device to perform a method comprising: programming memory cells coupled to first data lines in the first array of memory cells comprising loading user data into a dynamic data cache of the memory device coupled to the first data lines prior to programming the memory cells coupled to the first data lines; programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed; and programming memory cells coupled to data lines in the third array of memory cells with other flag data while programming the memory cells coupled to the first data lines in the first array of memory cells. ### Claim 17 (depends on 16) The memory device of claim 16, wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises: loading the other flag data into a portion of the dynamic data cache coupled to the data lines in the third array of memory cells while loading the user data into the dynamic data cache. ### Claim 18 A memory device, comprising: a first array of memory cells; a second array a memory cells; and control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: programming memory cells coupled to first data lines in the first array of memory cells; and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed; programming the memory cells coupled to the data lines in the second array of memory cells comprises programming data that includes both the flag data and other data associated with a particular page of data of the first array of memory cells. ### Claim 19 A memory device, comprising: a first array of memory cells; a second array of memory cells; and control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: programming memory cells coupled to first data lines in the first array of memory cells; and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed; wherein the flag data comprises a plurality of bytes of data; and wherein the plurality of bytes of data comprises a bit indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed and bytes providing additional information about the memory cells coupled to the second data lines in the first array of memory cells. ### Claim 20 A memo device, comprising: a first array of memory cells; a second array of memory cells; and control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising: programming memory cells coupled to first data lines in the first array of memory cells; and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed; wherein a first data line of the first data lines in the first array of memory cells and a second data line of the second data lines in the first array of memory cells are adjacent first and second data lines; and the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed is to be read concurrently with the memory cell coupled to the first data line of the adjacent first and second data lines.