# US 11,029,854 B2 · Memory controller for concurrently writing host data and garbage collected data and operating method thereof

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- Number: US 11,029,854 B2
- Document ID: US11029854B2
- Status: Granted
- Kind: B2
- Application number: 16/119,687
- Filed: 2018-08-31
- Published: 2019-07-25
- Granted: 2021-06-08
- Earliest claimed: 2018-01-24
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sung Kwan Hong
- Web page: https://patentgrep.com/patent/US11029854B2

## CPC

- G06F 3/0611: {in relation to response time}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 2212/1024: Latency reduction
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a processor. The buffer memory stores first data received from a host and second data received from the memory device. The processor controls the memory controller to generate a write command for programming the first data and the second data to the memory device.

## Claims

### Claim 1

A memory controller for controlling an operation of a memory device, the memory controller comprising:
a buffer memory; and
a processor configured to:
in response to a write request and first data received from a host, generate third data by comparing the first data and second data read from a victim memory block, and
generate a write command for programming the third data to the memory device.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein, the processor is configured to:
control the buffer memory to store the first data,
select the victim memory block of the memory device, and
generate a read command for reading valid page data stored in the victim memory block.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the processor is configured to control the buffer memory to store the second data.

### Claim 4 (depends on 3)

The memory controller of claim 3, wherein the processor is configured to generate the write command for programming the third data to the memory device after the second data is stored in the buffer memory.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the third data includes data generated by updating the second data based on the first data.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the third data includes the first data and the second data and is generated by deleting overlapping data in the first data and the second data.

### Claim 7 (depends on 1)

The memory controller of claim 1, wherein the processor is configured to:
determine whether garbage collection of the memory device is required by monitoring the memory device periodically, and store the second data in the buffer memory, in response to a determination that the garbage collection of the memory device is required.

### Claim 8 (depends on 1)

The memory controller of claim 1, wherein the first data and the second data are compared to identify whether the first data and the second data have the same content.

### Claim 9 (depends on 1)

The memory controller of claim 1, wherein the processor updates a mapping table after programming the third data to the memory device.

### Claim 10 (depends on 1)

The memory controller of claim 1, wherein the processor controls the memory device to erase the victim memory block, after programming the third data to the memory device.

### Claim 11

A method for operating a memory controller for controlling an operation of a memory device, the method comprising:
receiving a write request and first data from a host;
in response to the write request, controlling the memory device to read second data written in a victim memory block of the memory device;
generating third data by comparing the first data and the second data read from the victim memory block; and
controlling the memory device to write the third data in a target memory block of the memory device.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
controlling the memory device to erase the victim memory block.

### Claim 13 (depends on 11)

The method of claim 11, wherein the controlling of the memory device to read the second data written in the victim memory block of the memory device includes:
selecting, as the victim memory block, at least one memory block in which the number of invalid pages is larger than a set reference value based on valid and invalid pages written in memory blocks of the memory device;
generating a read command for reading valid page data in the victim memory block;
transferring the read command to the memory device; and
receiving the second data corresponding to the read command.

### Claim 14 (depends on 11)

The method of claim 11, wherein the third data includes the first data and the second data and is generated by deleting overlapping data in the first data and the second data.

### Claim 15 (depends on 11)

The method of claim 11, wherein the third data includes data generated by updating the second data based on the first data.

### Claim 16

A method for operating a memory controller for controlling an operation of a memory device, the method comprising:
determining whether garbage collection is required by monitoring the memory device;
in response to a determination that the garbage collection of the memory device is required, selecting a victim memory block of the memory device;
controlling the memory device to read first data stored in the victim memory block;
receiving a write request and second data from a host;
in response to the write request, generating third data by comparing the first data and the second data; and
controlling the memory device to write the third data in a target memory block of the memory device.

### Claim 17 (depends on 16)

The method of claim 16, wherein, the determining of whether the garbage collection is required comprises:
determining whether the number of free memory blocks in the memory device is less than or equal to a reference value, determining that the garbage collection of the memory device is required when the number of free memory blocks is less than or equal to the reference value, and determining that the garbage collection of the memory device is not required when the number of free memory blocks is greater than the reference value.

### Claim 18 (depends on 16)

The method of claim 16, wherein, in the selecting of the victim memory block of the memory device, at least one memory block in which the number of invalid pages is greater than a set reference value is selected as the victim memory block.

### Claim 19

A memory system comprising:
a memory device; and
a controller configured to control the memory device to perform a garbage collection operation of moving valid data of a victim memory block into a target memory block in the memory device, in response to a request of a write operation, while performing the write operation of storing write data into the target memory block,
wherein the controller gathers, during the garbage collection operation and the write operation, the valid data and the write data in a buffer in the controller and provides the gathered data to the memory device, and
wherein the gathered data is generated by comparing the valid data and the write data.