# US 11,029,852 B2 · Dedicated interface for coupling flash memory and dynamic random access memory

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- Number: US 11,029,852 B2
- Document ID: US11029852B2
- Status: Granted
- Kind: B2
- Application number: 15/378,473
- Filed: 2016-12-14
- Published: 2017-06-01
- Granted: 2021-06-08
- Earliest claimed: 2014-01-03
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: James Bauman
- Web page: https://patentgrep.com/patent/US11029852B2

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0614: {Improving the reliability of storage systems}
- G06F 3/0646: {Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/1072: {in multilevel memories}
- G06F 12/0862: with prefetch
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/4068: {Electrical coupling}
- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

## Claims

### Claim 1

A memory system, comprising:
a dynamic random access memory (DRAM);
a flash memory; and
a dedicated interface between the DRAM and the flash memory, wherein a first portion of the dedicated interface is implemented in the DRAM and a second portion of the dedicated interface is implemented in the flash memory, and further wherein the dedicated interface is only available for communication between the flash memory and the DRAM.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the first portion of the dedicated interface includes control logic to control operation of the dedicated interface.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the second portion of the dedicated interface includes multiple pipeline stages to perform pipelined execution of instructions in the flash memory.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the multiple pipeline stages are configured so that a plurality of requests can be processed concurrently by the dedicated interface.

### Claim 5 (depends on 1)

The memory system of claim 1, further comprising:
a DRAM interface between the DRAM and a processing device, wherein the dedicated interface is to provide prefetch data from the flash memory into the DRAM in response to a prefetch request provided over the DRAM interface prior to the DRAM receiving a request for the prefetched data.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the dedicated interface is to convey at least one page from the flash memory into the DRAM over the dedicated interface in response to a page-in instruction received by the DRAM over the DRAM interface.

### Claim 7

A method, comprising:
accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM), wherein a first portion of the dedicated interface is implemented in the DRAM and a second portion of the dedicated interface is implemented in the flash memory, and further wherein the dedicated interface is only available for communication between the flash memory and the DRAM.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
concurrently performing a plurality of requests in a plurality of pipeline stages of the second portion of the dedicated interface.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
controlling operations of the dedicated interface using control logic at the first portion of the dedicated interface.

### Claim 10 (depends on 7)

The method of claim 7, wherein accessing the flash memory further comprises:
accessing the flash memory in response to an instruction received over a DRAM interface between the DRAM and a processing device.

### Claim 11 (depends on 10)

The method of claim 10, wherein accessing the flash memory further comprises:
prefetching data from the flash memory into the DRAM via the dedicated interface in response to a prefetch request provided over the DRAM interface prior to the DRAM receiving a request for the prefetched data over the DRAM interface.

### Claim 12 (depends on 10)

The method of claim 10, wherein accessing the flash memory further comprises:
conveying at least one page from the flash memory into the DRAM over the dedicated interface in response to a page-in instruction received by the DRAM over the DRAM interface.

### Claim 13 (depends on 10)

The method of claim 10, wherein accessing the flash memory further comprises:
conveying at least one page from the DRAM into the flash memory over the dedicated interface in response to a page-out instruction received by the DRAM over the DRAM interface.

### Claim 14 (depends on 10)

The method of claim 10, wherein accessing the flash memory further comprises:
accessing the flash memory over a plurality of through silicon vias (TSVs) that couple the flash memory to the DRAM.

### Claim 15

A memory system, comprising:
a volatile memory;
a non-volatile memory; and
a dedicated interface between the volatile memory and the non-volatile memory, wherein a first portion of the dedicated interface is implemented in the volatile memory and a second portion of the dedicated interface is implemented in the non-volatile memory, and further wherein the dedicated interface is only available for communication between the volatile memory and the non-volatile memory.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein the first portion of the dedicated interface includes control logic to control operation of the dedicated interface.

### Claim 17 (depends on 15)

The memory system of claim 15, wherein the second portion of the dedicated interface includes multiple pipeline stages to perform pipelined execution of instructions in the non-volatile memory.

### Claim 18 (depends on 17)

The memory system of claim 17, wherein the multiple pipeline stages are configured so that a plurality of requests can be processed concurrently by the dedicated interface.

### Claim 19 (depends on 15)

The memory system of claim 15, further comprising:
a volatile memory interface between the volatile memory and a processing device, wherein the dedicated interface is to provide prefetch data from the non-volatile memory into the volatile memory in response to a prefetch request provided over the volatile memory interface prior to the volatile memory receiving a request for the prefetched data.

### Claim 20 (depends on 19)

The memory system of claim 19, wherein the dedicated interface is to convey at least one page from the non-volatile memory into the volatile memory over the dedicated interface in response to a page-in instruction received by the volatile over the volatile memory interface.