# US 11,029,748 B2 · Adaptive peripheral component interconnect express link substate initiation for optimal performance and power savings > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,748 B2 - Document ID: US11029748B2 - Status: Granted - Kind: B2 - Application number: 15/070,381 - Filed: 2016-03-15 - Published: 2017-09-21 - Granted: 2021-06-08 - Earliest claimed: 2016-03-15 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Neven Klacar; Muralidhar Krishnamoorthy; Hariharan Sukumar - Web page: https://patentgrep.com/patent/US11029748B2 ## CPC - G06F 1/3278: {Power saving in modem or I/O interface} - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/3215: Monitoring of peripheral devices - G06F 1/3237: by disabling clock generation or distribution - G06F 1/3253: {Power saving in bus} - G06F 13/102: {where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52)} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4068: {Electrical coupling} - G06F 13/4291: {using a clocked protocol} - G06F 13/4295: {using an embedded synchronisation} - G06F 2213/0026: PCI express - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number. ## Claims ### Claim 1 A method performed by a controller of a Peripheral Component Interconnect Express (PCIe) interface, comprising: determining that a first burst of data is being transmitted on a PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol; configuring a timer to signal when an entry latency period has elapsed after determining that the PCIe link has entered an idle state after completing transmission of a first packet in the plurality of packets; causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission; increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and updating the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst. ### Claim 2 (depends on 1) The method of claim 1, wherein increasing the entry latency period comprises: doubling the entry latency period. ### Claim 3 (depends on 1) The method of claim 1, further comprising: decreasing the entry latency period when the PCIe interface does not enter the low-power state between transmissions of a pair of packets in the plurality of packets. ### Claim 4 (depends on 1) The method of claim 1, further comprising: decreasing the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data; and updating the second threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated second threshold to be used in the subsequent second burst. ### Claim 5 (depends on 4) The method of claim 4, wherein decreasing the entry latency period comprises: halving the entry latency period. ### Claim 6 (depends on 4) The method of claim 4, wherein decreasing the entry latency period comprises: restoring a previous time period used for the entry latency period. ### Claim 7 (depends on 1) The method of claim 1, wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises: disabling one or more circuits of a transceiver coupled to the PCIe interface. ### Claim 8 (depends on 1) The method of claim 1, wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises: disabling or gating a clock signal used by one or more circuits of the PCIe interface. ### Claim 9 (depends on 1) The method of claim 1, wherein causing one or more circuits of the PCIe interface to enter the low-power state comprises: causing circuits in two or more devices coupled to the PCIe interface to enter the low-power state. ### Claim 10 An apparatus comprising: a Peripheral Component Interconnect Express (PCIe) interface adapted to couple the apparatus to a PCIe link; and a controller configured to determine that a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol, and wherein during transmission of the first burst of data the controller is further configured to: determine when the PCIe link has entered an idle state; enable a timer adapted to signal when an entry latency period has elapsed after determining that the PCIe link has entered the idle state after completing transmission of a first packet in the plurality of packets; cause one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission; increase the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and update the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: increase the entry latency period comprises double the entry latency period. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: decrease the entry latency period when the PCIe interface does not enter the low-power state between transmissions of a pair of packets in the plurality of packets. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: decrease the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data; and update the second threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated second threshold to be used in the subsequent second burst. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the controller is configured to: decrease the entry latency period by halving the entry latency period. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the controller is configured to: decrease the entry latency period by restoring a previous time period used for the entry latency period. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: cause the one or more circuits of the PCIe interface to enter the low-power state by disabling one or more circuits of a transceiver coupled to the PCIe interface. ### Claim 17 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: cause the one or more circuits of the PCIe interface to enter the low-power state by disabling or gating a clock signal used by one or more circuits of the PCIe interface. ### Claim 18 (depends on 10) The apparatus of claim 10, wherein the controller is configured to: cause the one or more circuits of the PCIe interface to enter the low-power state by causing circuits in two or more devices coupled to the PCIe interface to enter the low-power state. ### Claim 19 An apparatus comprising: means for determining activity on a PCIe link, including determining when a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol; means for managing power consumption in a Peripheral Component Interconnect Express (PCIe) interface, and configured to transition the PCIe interface between at least a first state and a second state; means for configuring a timer, wherein the means for configuring the timer is adapted to signal when an entry latency period has elapsed after the means for determining activity on the PCIe link has determined that the PCIe link has entered an idle state between transmissions of a first pair of packets in the first burst of data transmitted on the PCIe link; and means for modifying the entry latency period based on a number of entries of the PCIe interface to a low-power state that occurs during transmission of the first burst of data, wherein the means for modifying the entry latency period is configured to: increase the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and update the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst, wherein the means for managing power consumption is configured to cause one or more circuits of the PCIe interface to enter the low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the means for modifying the entry latency period is configured to: increase the entry latency period by doubling the entry latency period. ### Claim 21 (depends on 19) The apparatus of claim 19, wherein the means for modifying the entry latency period is configured to: halve the entry latency period when the PCIe interface does not enter the low-power state during transmission between transmissions of a second pair of packets in the plurality of packets. ### Claim 22 (depends on 19) The apparatus of claim 19, wherein the means for modifying the entry latency period is configured to: restore a previous time period used for the entry latency period when the PCIe interface does not enter the low-power state during transmission of the first burst of data. ### Claim 23 (depends on 19) The apparatus of claim 19, wherein the means for modifying the entry latency period is configured to: halve the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data. ### Claim 24 (depends on 19) The apparatus of claim 19, wherein the means for modifying the entry latency period is configured to: restore a previous time period used for the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data. ### Claim 25 (depends on 19) The apparatus of claim 19, wherein the means for managing power consumption is configured to: disable a transceiver coupled to the PCIe interface when the timer signals that the entry latency period has elapsed before the PCIe link becomes active. ### Claim 26 (depends on 19) The apparatus of claim 19, wherein the means for managing power consumption is configured to: gate a clock signal used by one or more circuits of the PCIe interface when the timer signals that the entry latency period has elapsed before the PCIe link becomes active. ### Claim 27 (depends on 19) The apparatus of claim 19, wherein the means for managing power consumption is configured to: cause circuits in two or more devices coupled to the PCIe interface to enter the low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active. ### Claim 28 A non-transitory processor-readable storage medium comprising code for: determining that a first burst of data is being transmitted on a Peripheral Component Interconnect Express (PCIe) link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol; configuring a timer to signal when an entry latency period has elapsed after determining that the PCIe link has entered an idle state after completing transmission of a first packet in the plurality of packets; causing one or more circuits of a PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission; increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data; and updating the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst. ### Claim 29 (depends on 28) The storage medium of claim 28, comprising code for: decreasing the entry latency period when the number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data is less than a second threshold that defines a minimum number of entries into the low-power state per burst of data; and updating the second threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated second threshold to be used in the subsequent second burst. ### Claim 30 (depends on 29) The storage medium of claim 29, comprising code for: causing circuits in two or more devices coupled to the PCIe interface to enter the low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active.