# US 11,029,746 B2 · Dynamic power management network for memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,746 B2 - Document ID: US11029746B2 - Status: Granted - Kind: B2 - Application number: 16/427,280 - Filed: 2019-05-30 - Published: 2020-12-03 - Granted: 2021-06-08 - Earliest claimed: 2019-05-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Giuseppe Cariello; Jonathan S. Parry - Web page: https://patentgrep.com/patent/US11029746B2 ## CPC - G06F 1/3268: {Power saving in hard disk drive} - G06F 1/3221: of disk drive devices - G06F 1/3225: of memory devices - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 3/0625: {Power saving in storage systems} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0673: {Single storage device} - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Techniques for managing power usage in a memory subsystem are described. An operation type of each of a plurality of operations queued against one or more of a plurality of memory components is obtained. It is determined that at least two of the plurality of operations can be performed in parallel and that a first configuration of the plurality of memory components does not allow the at least two operations to be performed in parallel, the first configuration including a first set of power management cohorts. An interconnection of the plurality of memory components is reconfigured to change from the first configuration to a second configuration of the of the plurality of memory components, the second configuration including a second set of power management cohorts that allow the at least two operations to be performed in parallel. ## Claims ### Claim 1 A method comprising: obtaining an operation type of each of a plurality of operations queued against one or more of a plurality of memory components; determining that at least two of the plurality of operations can be performed in parallel; determining that a first configuration of the plurality of memory components does not allow the at least two operations to be performed in parallel, the first configuration including a first set of power management cohorts; and altering an interconnection of the plurality of memory components to change from the first configuration to a second configuration of the of the plurality of memory components, the second configuration including a second set of power management cohorts that allow the at least two operations to be performed in parallel. ### Claim 2 (depends on 1) The method of claim 1, wherein altering the interconnection comprises closing a first set of one or more switches to couple a clock signal generated by a first memory component of a first power management cohort to each of the other memory components of the first power management cohort. ### Claim 3 (depends on 2) The method of claim 2, wherein altering the interconnection comprises closing a second set of one or more switches to couple a data signal amongst a plurality of memory components of the first power management cohort. ### Claim 4 (depends on 1) The method of claim 1, wherein only a single memory component of a first power management cohort of the second set of power management cohorts has a queued high-power operation. ### Claim 5 (depends on 1) The method of claim 1, wherein altering the interconnection is conditioned on a flag accessible by a host system. ### Claim 6 (depends on 1) The method of claim 1, wherein the operation type is one of at least a high-power operation and a low-power operation. ### Claim 7 (depends on 1) The method of claim 1, wherein: the second set of power management cohorts includes a first power management cohort; and none of a plurality of memory components of the first power management cohort have a queued high-power operation. ### Claim 8 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: obtain an operation type of each of a plurality of operations queued against one or more of a plurality of memory components; determine that at least two of the plurality of operations can be performed in parallel; determine that a first configuration of the plurality of memory components does not allow the at least two operations to be performed in parallel, the first configuration including a first set of power management cohorts; and alter an interconnection of the plurality of memory components to change from the first configuration to a second configuration of the plurality of memory components, the second configuration including a second set of power management cohorts that allow the at least two operations to be performed in parallel. ### Claim 9 (depends on 8) The non-transitory computer-readable storage medium of claim 8, wherein altering the interconnection the processing device is further to close a first set of one or more switches to couple a clock signal generated by a first memory component of a first power management cohort to each of the other memory components of the first power management cohort. ### Claim 10 (depends on 9) The non-transitory computer-readable storage medium of claim 9, wherein altering the interconnection the processing device is further to close a second set of one or more switches to couple a data signal amongst a plurality of memory components of the first power management cohort. ### Claim 11 (depends on 8) The non-transitory computer-readable storage medium of claim 8, wherein only a single memory component of a first power management cohort of the second set of power management cohorts has a queued high-power operation. ### Claim 12 (depends on 8) The non-transitory computer-readable storage medium of claim 8, wherein altering the interconnection is conditioned on a flag accessible by a host system. ### Claim 13 (depends on 8) The non-transitory computer-readable storage medium of claim 8, wherein the operation type is one of at least a high-power operation and a low-power operation. ### Claim 14 (depends on 8) The non-transitory computer-readable storage medium of claim 8, wherein: the second set of power management cohorts includes a first power management cohort; and none of a plurality of memory components of the first power management cohort have a queued high-power operation. ### Claim 15 A system comprising: a plurality of memory components; and a processing device, operatively coupled with the plurality of memory components, to: obtain an operation type of each of a plurality of operations queued against one or more of the plurality of memory components; and alter, based on the operation type of each of the plurality of operations, an interconnection of the plurality of memory components to change a grouping of the plurality of memory components from a first set of power management cohorts to a second set of power management cohorts that is different from the first set. ### Claim 16 (depends on 15) The system of claim 15, wherein altering the interconnection the processing device is further to close a first set of one or more switches to couple a clock signal generated by a first memory component of a first power management cohort to each of the other memory components of the first power management cohort. ### Claim 17 (depends on 16) The system of claim 16, wherein altering the interconnection the processing device is further to close a second set of one or more switches to couple a data signal amongst a plurality of memory components of the first power management cohort. ### Claim 18 (depends on 15) The system of claim 15, wherein only a single memory component of a first power management cohort of the second set of power management cohorts has a queued high-power operation. ### Claim 19 (depends on 15) The system of claim 15, wherein altering the interconnection is conditioned on a flag accessible by a host system. ### Claim 20 (depends on 15) The system of claim 15, wherein the operation type is one of at least a high-power operation and a low-power operation.