# US 11,029,742 B2 · Mitigating voltage droop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,742 B2 - Document ID: US11029742B2 - Status: Granted - Kind: B2 - Application number: 16/371,202 - Filed: 2019-04-01 - Published: 2020-10-01 - Granted: 2021-06-08 - Earliest claimed: 2019-04-01 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Tobias Webel; Preetham M Lobo; Alper Buyuktosunoglu; Ramon Bertran Monfort; Pradeep Bhadravati Parashurama; Archit Kapoor - Web page: https://patentgrep.com/patent/US11029742B2 ## CPC - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate. ## Claims ### Claim 1 A computer-implemented method comprising: performing a first determination that a timing margin is less than a first threshold, wherein the first threshold comprises a high-edge threshold and a low-edge threshold, and wherein performing the first determination comprises: generating a history of critical-path monitor sensor signals within a plurality of sampling windows, wherein the history comprises a plurality of high-edge critical-path monitor (CPM) signals and a plurality of low-edge CPM signals; identifying the high-edge CPM signals based on the high-edge threshold and the low-edge threshold; identifying the low-edge CPM signals based on the high-edge threshold and the low-edge threshold; and determining that one of the low-edge CPM signals occurs after one of the high-edge CPM signals within the history; performing a second determination that an increase in processor activity exceeds a second threshold; determining that a voltage droop is indicated based on the first determination and the second determination; and signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate based on the determination. ### Claim 2 (depends on 1) The method of claim 1, wherein performing the second determination comprises: generating a history of digital power-proxy sensor signals within a plurality of sampling windows; totaling a first half of the history; totaling a second half of the history; subtracting the totaled second half from the totaled first half to generate the increase in processor activity; and comparing the increase in processor activity to the second threshold. ### Claim 3 (depends on 2) The method of claim 2, wherein the history of digital power-proxy signals comprises eight sampling windows. ### Claim 4 (depends on 3) The method of claim 3, wherein the first half of the history of digital power-proxy signals comprises a first four of the eight sampling windows, and the second half of the history of digital power-proxy signals comprises a last four of the eight sampling windows. ### Claim 5 (depends on 2) The method of claim 2, the method further comprising generating a sampling window comprising a predetermined number of clock cycles, wherein at an end of the sampling window: the history of critical-path monitor sensor signals is shifted by one; and the history of digital power-proxy sensor signals is shifted by one. ### Claim 6 (depends on 5) The method of claim 5, wherein at the end of the sampling window: a current critical-path monitor sensor signal is shifted into the history of critical-path monitor signals; and a current digital power-proxy sensor signal is shifted into the history of digital power-proxy sensor signals. ### Claim 7 An apparatus comprising an electric circuit configured to: perform a first determination that a timing margin is less than a first threshold, wherein the first threshold comprises a high-edge threshold and a low-edge threshold, and wherein performing the first determination comprises: generating a history of critical-path monitor sensor signals within a plurality of sampling windows, wherein the history comprises a plurality of high-edge critical-path monitor (CPM) signals and a plurality of low-edge CPM signals; identifying the high-edge CPM signals based on the high-edge threshold and the low-edge threshold; identifying the low-edge CPM signals based on the high-edge threshold and the low-edge threshold; and determining that one of the low-edge CPM signals occurs after one of the high-edge CPM signals within the history; perform a second determination that an increase in processor activity exceeds a second threshold; determine that a voltage droop is indicated based on the first determination and the second determination; and signal a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein performing the second determination comprises: generating a history of digital power-proxy sensor signals within a plurality of sampling windows; totaling a first half of the history; totaling a second half of the history; subtracting the totaled second half from the totaled first half to generate the increase in processor activity; and comparing the increase in processor activity to the second threshold. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the history of digital power-proxy signals comprises eight sampling windows. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first half of the history of digital power-proxy signals comprises a first four of the eight sampling windows, and the second half of the history of digital power-proxy signals comprises a last four of the eight sampling windows. ### Claim 11 (depends on 8) The apparatus of claim 8, the apparatus further configured to generate a sampling window comprising a predetermined number of clock cycles, wherein at an end of the sampling window: the history of critical-path monitor sensor signals is shifted by one; and the history of digital power-proxy sensor signals is shifted by one. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein at the end of the sampling window: a current critical-path monitor sensor signal is shifted into the history of critical-path monitor signals; and a current digital power-proxy sensor signal is shifted into the history of digital power-proxy sensor signals. ### Claim 13 A system comprising: a computer processing circuit comprising a plurality of cores; and a voltage droop mitigation circuit, which, when activated, is configured to: perform a first determination that a timing margin is less than a first threshold, wherein the first threshold comprises a high-edge threshold and a low-edge threshold, and wherein performing the first determination comprises: generating a history of critical-path monitor sensor signals within a plurality of sampling windows, wherein the history comprises a plurality of high-edge critical-path monitor (CPM) signals and a plurality of low-edge CPM signals; identifying the high-edge CPM signals based on the high-edge threshold and the low-edge threshold; identifying the low-edge CPM signals based on the high-edge threshold and the low-edge threshold; and determining that one of the low-edge CPM signals occurs after one of the high-edge CPM signals within the history; perform a second determination that an increase in processor activity exceeds a second threshold; determine that a voltage droop is indicated based on the first determination and the second determination; and signal a plurality of throttling circuits corresponding to the plurality of cores to actuate. ### Claim 14 (depends on 13) The system of claim 13, wherein performing the second determination comprises: generating a history of digital power-proxy sensor signals within a plurality of sampling windows; totaling a first half of the history of digital power-proxy signals; totaling a second half of the history of digital power-proxy signals; subtracting the totaled second half from the totaled first half to generate the increase in processor activity; and comparing the increase in processor activity to the second threshold. ### Claim 15 (depends on 14) The system of claim 14, wherein the history of digital power-proxy signals comprises eight sampling windows, and wherein the first half of the history of digital power-proxy signals comprises a first four of the eight sampling windows, and wherein the second half of the history of digital power-proxy signals comprises a last four of the eight sampling windows. ### Claim 16 (depends on 14) The system of claim 14, wherein the voltage droop mitigation circuit, when activated, is further configured to generate a sampling window comprising a predetermined number of clock cycles, wherein at an end of the sampling window: the history of critical-path monitor sensor signals is shifted by one; and the history of digital power-proxy sensor signals is shifted by one. ### Claim 17 (depends on 16) The system of claim 16, wherein at the end of the sampling window: a current critical-path monitor sensor signal is shifted into the history of critical-path monitor signals; and a current digital power-proxy sensor signal is shifted into the history of digital power-proxy sensor signals.