# US 11,029,720 B2 · Area-efficient scalable memory read-data multiplexing and latching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,720 B2 - Document ID: US11029720B2 - Status: Granted - Kind: B2 - Application number: 16/386,070 - Filed: 2019-04-16 - Published: 2020-10-22 - Granted: 2021-06-08 - Earliest claimed: 2019-04-16 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Amir Javidi; Daniel Cummings; Glenn Starnes - Web page: https://patentgrep.com/patent/US11029720B2 ## CPC - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G11C 11/419: Read-write [R-W] circuits - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/324: by lowering clock frequency - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/106: {Data output latches} - G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM} - G11C 7/1087: {Data input latches} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path. ## Claims ### Claim 1 An apparatus comprising: a first circuitry having an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output; a second circuitry having a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path; and a third circuitry having an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first clocked inverter has a positive-clock input connected to a first clock signal path and a negative-clock input connected to a second clock signal path; wherein the second clocked inverter has a positive-clock input connected to the second clock signal path and a negative-clock input connected to the first clock signal path; and wherein the second clock signal path is to carry an inverse of a signal carried on the first clock signal path. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the sensed memory bit is a first sensed memory bit, wherein the apparatus comprising: an additional circuitry having an output coupled to the shared-read-data signal path, the additional circuitry either driving its output to a value based on a second sensed memory bit, or not driving its output. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the shared-read-data signal path is a first shared-read-data signal path, wherein the apparatus comprising: an additional circuitry having a third clocked inverter and a fourth clocked inverter cross-coupled with the third clocked inverter, an input of the third clocked inverter being coupled to a second shared-read-data signal path, and an output of the third clocked inverter being coupled to the inverse-data signal path. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the third clocked inverter has a positive-clock input connected to a third clock signal path and a negative-clock input connected to a fourth clock signal path; wherein the fourth clocked inverter has a positive-clock input connected to the fourth clock signal path and a negative-clock input connected to the third clock signal path; and wherein the fourth clock signal path carries an inverse of a signal carried on the third clock signal path. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first clock signal path and the third clock signal path are independently driven. ### Claim 7 (depends on 5) The apparatus of claim 5, comprising: a clock circuitry having a first output carrying an OR of the first clock signal path and the third clock signal path, and a second output carrying an inverse of the first output. ### Claim 8 (depends on 7) The apparatus of claim 7, comprising: a clocked latching circuitry having a data input connected to the inverse-data signal path, a data output connected to the inverse-data signal path, a positive-clock input connected to the second output of the clock circuitry, and a negative-clock input connected to the first output of the clock circuitry. ### Claim 9 An apparatus comprising: a driver circuitry having a sense amplifier and an output coupled to a shared-read-data signal path, the driver circuitry to either drive its output to a value of a sensed memory bit during a read operation of its sense amplifier, or not drive its output during a standby mode of its sense amplifier; a receiver-and-keeper circuitry having cross-coupled clocked inverters, one of the clocked inverters having an input coupled to the shared-read-data signal path and an output coupled to an inverse-data signal path; and an inverter having an input coupled to the inverse-data signal data path and an output coupled to a data signal path. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein a first clocked inverter of the receiver-and-keeper circuitry has a positive-clock input connected to a first clock signal path and a negative-clock input connected to a second clock signal path; wherein a second clocked inverter of the receiver-and-keeper circuitry has a positive-clock input connected to the second clock signal path and a negative-clock input connected to the first clock signal path; and wherein the second clock signal path carries an inverse of a signal carried on the first clock signal path. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the driver circuitry is a first driver circuitry, and wherein the sensed memory bit is a first sensed memory bit, wherein the apparatus comprising: a second driver circuitry having a sense amplifier and an output coupled to the shared-read-data signal path, the second driver circuitry to either drive its output to a value of a second sensed memory bit during a read operation of its sense amplifier, or not drive its output during a standby mode of its sense amplifier. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the shared-read-data signal path is a first shared-read-data signal path, and wherein the receiver-and-keeper circuitry is a first receiver-and-keeper circuitry, wherein the apparatus comprising: a second receiver-and-keeper circuitry having cross-coupled clocked inverters, one of the clocked inverters having an input coupled to a second shared-read-data signal path and an output coupled to the inverse-data signal path. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein a first clocked inverter of the second receiver-and-keeper circuitry has a positive-clock input connected to a third clock signal path and a negative-clock input connected to a fourth clock signal path; wherein a second clocked inverter of the second receiver-and-keeper circuitry has a positive-clock input connected to the fourth clock signal path and a negative-clock input connected to the third clock signal path; and wherein the fourth clock signal path carries an inverse of a signal carried on the third clock signal path. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the first clock signal path and the third clock signal path are independently driven. ### Claim 15 (depends on 13) The apparatus of claim 13, comprising: a clock circuitry having a first output carrying an OR of the first clock signal path and the third clock signal path, and a second output carrying an inverse of the first output. ### Claim 16 (depends on 15) The apparatus of claim 15, comprising: a clocked latching circuitry having a data input connected to the inverse-data signal path, a data output connected to the inverse-data signal path, a positive-clock input connected to the second output of the clock circuitry, and a negative-clock input connected to the first output of the clock circuitry. ### Claim 17 A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including: a first circuitry having an output coupled to a shared-read-data signal path, the first circuitry to either drive its output to a value based on a sensed memory bit, or not drive its output; a second circuitry having a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path; and a third circuitry having an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path. ### Claim 18 (depends on 17) The system of claim 17, wherein the first clocked inverter has a positive-clock input connected to a first clock signal path and a negative-clock input connected to a second clock signal path; wherein the second clocked inverter has a positive-clock input connected to the second clock signal path and a negative-clock input connected to the first clock signal path; and wherein the second clock signal path is to carry an inverse of a signal carried on the first clock signal path. ### Claim 19 (depends on 17) The system of claim 17, wherein the sensed memory bit is a first sensed memory bit, wherein the processor comprising: an additional circuitry having an output coupled to the shared-read-data signal path, the additional circuitry to either drive its output to a value based on a second sensed memory bit, or not drive its output. ### Claim 20 (depends on 17) The system of claim 17, wherein the shared-read-data signal path is a first shared-read-data signal path, wherein the processsor comprising: an additional circuitry having a third clocked inverter and a fourth clocked inverter cross-coupled with the third clocked inverter, an input of the third clocked inverter being coupled to a second shared-read-data signal path, and an output of the third clocked inverter being coupled to the inverse-data signal path.