# US 11,029,659 B2 · Method and apparatus for remote field programmable gate array processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,659 B2 - Document ID: US11029659B2 - Status: Granted - Kind: B2 - Application number: 16/314,401 - Filed: 2016-06-30 - Published: 2019-05-23 - Granted: 2021-06-08 - Earliest claimed: 2016-06-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Nicolas A. Salhuana; Karthik Kumar; Thomas Willhalm; Francesc Guim Bernat; Narayan Ranganathan - Web page: https://patentgrep.com/patent/US11029659B2 ## CPC - G05B 19/0426: {Programming the control sequence} - G06F 8/44: {Encoding} - G06F 8/456: {Parallelism detection} - G06F 9/5044: {considering hardware capabilities} - G06F 15/7867: {with reconfigurable architecture} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17732: Macroblocks - G05B 2219/21109: Field programmable gate array, fpga as I-O module - G06F 2209/509: Offload - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric. ## Claims ### Claim 1 An apparatus comprising: a hardware fabric controller of a first computing node, the fabric controller to: receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the fabric controller is to instruct the FPGA to execute the kernel by sending a message from the fabric controller to the FPGA, wherein the message does not pass through a processing core of the first computing node. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the fabric controller is further to initiate programming of a data structure on the FPGA in response to a request from the second computing node, the data structure comprising information to configure logic of the FPGA to enable the FPGA to implement the kernel. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the fabric controller initiates the programming of the data structure in response to receiving the data structure from the second computing node. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the fabric controller initiates the programming of the data structure in response to receiving the request to execute the kernel from the second computing node. ### Claim 6 (depends on 3) The apparatus of claim 3, wherein the data structure is sent from the fabric controller to the FPGA without passing through a processing core of the first computing node. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the fabric controller is further to direct the FPGA to store the result of the execution of the kernel in a memory of the first computing node. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the fabric controller is further to store a plurality of kernel entries, wherein a kernel entry identifies a kernel programmed on an FPGA managed by the fabric controller. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein a first set of the kernel entries is reserved for the first computing node and a second set of the kernel entries is reserved for one or more other computing nodes, the one or more other computing nodes comprising the second computing node. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the fabric controller is further to evict a kernel from the FPGA in response to a request to program the kernel. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the kernel that is evicted is selected based on a determination that the kernel is not being used. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the kernel that is evicted is selected based on a determination of time elapsed since the kernel was last executed. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein the kernel that is evicted is selected based on a determination that the kernel has been executed at least once. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the fabric controller is to instruct the FPGA to execute the kernel in response to a determination that the FPGA is not currently executing the kernel. ### Claim 15 A method comprising: receiving, at a hardware fabric controller of a first computing node from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instructing the FPGA to execute the kernel; and sending a result of the execution of the kernel to the second computing node via the network fabric. ### Claim 16 (depends on 15) The method of claim 15, wherein instructing the FPGA to execute the kernel comprises sending a message from the fabric controller to the FPGA, wherein the message does not pass through a processing core of the first computing node. ### Claim 17 (depends on 15) The method of claim 15, further comprising initiating programming of a data structure on the FPGA in response to a request from the second computing node, the data structure comprising information to configure logic of the FPGA to enable the FPGA to implement the kernel. ### Claim 18 A system comprising: a first computing node comprising: a processor core to generate a request to execute a kernel; and a first fabric controller hardware to receive the request to execute the kernel from the processor core; and a second computing node comprising: a field programmable gate array (FPGA); and a second fabric controller to: receive the request to execute the kernel from the first fabric controller hardware over a network fabric coupling the second computing node to the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the first computing node via the network fabric. ### Claim 19 (depends on 18) The system of claim 18, wherein instructing the FPGA to execute the kernel comprises sending a message from the second fabric controller to the FPGA, wherein the message does not pass through a processing core of the second computing node. ### Claim 20 (depends on 18) The system of claim 18, further comprising one or more of: a battery communicatively coupled to the first computing node; or a display communicatively coupled to the first computing node.