# US 11,029,572 B2 · Display device

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- Number: US 11,029,572 B2
- Document ID: US11029572B2
- Status: Granted
- Kind: B2
- Application number: 16/821,174
- Filed: 2020-03-17
- Published: 2020-07-09
- Granted: 2021-06-08
- Earliest claimed: 2017-01-11
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Kei Takahashi
- Web page: https://patentgrep.com/patent/US11029572B2

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1343: Electrodes {(reflective electrodes G02F1/133553)}
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

To achieve a display device that is suitable for increasing in size and to provide a high-resolution display device. In the display device, three or more adjacent gate lines are supplied with the same selection signal. Three or more pixels that adjoin in the column direction are connected to different source lines. In each of the pixels, a transistor including a semiconductor layer is disposed. An inner source line among three or more source lines is disposed to overlap with a conductive layer that functions as a pixel electrode. Part of the semiconductor layer of the transistor is provided between the outer source line and a source line adjacent to the outer source line.

## Claims

### Claim 1

A display device comprising:
a pixel area, the pixel area comprising:
a first source line;
a second source line adjacent to the first source line;
a third source line adjacent to the second source line;
a gate line;
a transistor; and
a pixel electrode;
a first gate driver; and
a second gate driver,
wherein the gate line is electrically connected to the first gate driver and the second gate driver,
wherein the pixel area is between the first gate driver and the second gate driver in a plan view,
wherein a gate of the transistor is electrically connected to the gate line, one of a source and a drain of the transistor is electrically connected to the first source line, the other of the source and the drain of the transistor is electrically connected to the pixel electrode,
wherein the pixel electrode overlaps with the second source line and the third source line,
wherein the pixel electrode does not overlap with the first source line, and
wherein a distance between the first source line and the second source line is larger than a distance between the second source line and the third source line.

### Claim 2 (depends on 1)

The display device according to claim 1, further comprising:
a fourth source line adjacent to the third source line,
wherein the pixel electrode does not overlap with the fourth source line.

### Claim 3 (depends on 1)

The display device according to claim 1, further comprising:
a liquid crystal over the pixel electrode.

### Claim 4 (depends on 1)

The display device according to claim 1, wherein a semiconductor layer of the transistor comprises an oxide semiconductor comprising indium, gallium, and zinc.

### Claim 5 (depends on 1)

The display device according to claim 1, wherein a semiconductor layer of the transistor comprises amorphous silicon.

### Claim 6 (depends on 1)

The display device according to claim 1, further comprising:
a capacitor comprising a first electrode and a second electrode electrically connected to the pixel electrode,
wherein the second electrode is between the first source line and the second source line.

### Claim 7

A display device comprising:
a pixel area, the pixel area comprising:
a first source line;
a second source line adjacent to the first source line;
a third source line adjacent to the second source line;
a fourth source line adjacent to the third source line;
a gate line;
a transistor; and
a pixel electrode;
a first source driver; and
a second source driver,
wherein the first source line and the third source line are electrically connected to the first source driver,
wherein the second source line and the fourth source line are electrically connected to the second source driver,
wherein a gate of the transistor is electrically connected to the gate line, one of a source and a drain of the transistor is electrically connected to the first source line, the other of the source and the drain of the transistor is electrically connected to the pixel electrode,
wherein the pixel electrode overlaps with the second source line and the third source line,
wherein the pixel electrode does not overlap with the first source line and the fourth source line, and
wherein a distance between the first source line and the second source line is larger than a distance between the second source line and the third source line.

### Claim 8 (depends on 7)

The display device according to claim 7, further comprising:
a first gate driver; and
a second gate driver,
wherein the gate line is electrically connected to the first gate driver and the second gate driver, and
wherein the pixel area is between the first gate driver and the second gate driver in a plan view.

### Claim 9 (depends on 7)

The display device according to claim 7, wherein the pixel area is between the first source driver and the second source driver in a plan view.

### Claim 10 (depends on 7)

The display device according to claim 7, further comprising:
a liquid crystal over the pixel electrode.

### Claim 11 (depends on 7)

The display device according to claim 7, wherein a semiconductor layer of the transistor comprises an oxide semiconductor comprising indium, gallium, and zinc.

### Claim 12 (depends on 7)

The display device according to claim 7, wherein a semiconductor layer of the transistor comprises amorphous silicon.

### Claim 13 (depends on 7)

The display device according to claim 7, further comprising:
a capacitor comprising a first electrode and a second electrode electrically connected to the pixel electrode,
wherein the second electrode is between the first source line and the second source line.