# US 11,029,355 B2 · Direct measurement test structures for measuring static random access memory static noise margin

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,029,355 B2
- Document ID: US11029355B2
- Status: Granted
- Kind: B2
- Application number: 16/374,355
- Filed: 2019-04-03
- Published: 2020-10-08
- Granted: 2021-06-08
- Earliest claimed: 2019-04-03
- Assignees: The Boeing Company
- Applicants: The Boeing Company
- Inventors: Mark Yao; Manuel F. Cabanas-Holmen; Ethan H. Cannon
- Web page: https://patentgrep.com/patent/US11029355B2

## CPC

- G01R 31/2626: {for measuring noise (measuring noise factor in general G01R29/26)}
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G01R 23/20: Measurement of non-linear distortion
- G01R 27/28: Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response (in line transmission systems H04B3/46)
- G01R 29/26: Measuring noise figure; Measuring signal-to-noise ratio
- G01R 31/275: {for testing individual semiconductor components within integrated circuits}
- G01R 31/2834: {Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736)}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 11/418: Address circuits
- G11C 11/419: Read-write [R-W] circuits
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C 29/50016: {of retention}
- G11C 29/54: Arrangements for designing test circuits, e.g. design for test [DFT] tools
- G11C 29/56008: {Error analysis, representation of errors}
- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 11/417: for memory cells of the field-effect type
- G11C 2029/0401: {in embedded memories}
- G11C 2029/0403: {during or with feedback to manufacture}
- G11C 2029/5004: {Voltage}
- G11C 2029/5602: {Interface to device under test}
- G11C 2029/5604: {Display of error information}
- H04B 3/46: Monitoring; Testing
- H04B 17/336: Signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR]
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H04B: TRANSMISSION

## Abstract

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

## Claims

### Claim 1

A test structure for directly measuring a stability of one or more static random access memory (SRAM) cells in an Integrated Circuit (IC) device, the test structure comprising, for each SRAM cell of the one or more SRAM cells:
a first transmission gate (TG) electrically coupled to a first side of a cut off in the SRAM cell;
a second TG electrically coupled to a second side of the cut off;
a first external pin electrically coupled to the first TG and a second external pin electrically coupled to the second TG; and
a first internal node electrically coupled to the first TG and a second internal node electrically coupled to the second TG, wherein:
the cut off provides an electrical open between the first side of the cut off and the second side of the cut off; and
the first internal node is electrically coupled to the first external pin and the second internal node is electrically coupled to the second external pin.

### Claim 2 (depends on 1)

The test structure of claim 1, wherein the IC device is fabricated in a complementary metal-oxide-semiconductor (CMOS) process.

### Claim 3 (depends on 1)

The test structure of claim 1, wherein the first internal node is electrically coupled to the first external pin through the first TG and the second internal node is electrically coupled to the second external pin through the second TG.

### Claim 4 (depends on 1)

The test structure of claim 1, wherein the first TG, the second TG, and the SRAM cell each comprise a same transistor type.

### Claim 5 (depends on 1)

The test structure of claim 1, further comprising an array of a plurality of test structures, each of the plurality of test structures addressing a respective one of a plurality of SRAM cells, wherein each of the plurality of test structures are operable to measure static noise margin (SNM) of a respective one of the plurality of SRAM cells.

### Claim 6 (depends on 1)

The test structure of claim 1, wherein the one or more SRAM cells include one or more of a 6-cell SRAM cell, a 7-cell SRAM cell, an 8-cell SRAM cell, and a Dual Interlocked Cell (DICE) SRAM cell.

### Claim 7 (depends on 1)

The test structure of claim 1, further comprising measurement circuitry, wherein calibration of voltage drop in the measurement circuitry includes:
using a word line (WL) decoder and column multiplexer peripheral circuitry of the SRAM cell; and
the measurement circuitry further includes connecting wires that electrically couple the first TG to the second TG.

### Claim 8 (depends on 1)

The test structure of claim 1, wherein feedback between the first internal node and the second internal node is broken at the cut off.

### Claim 9

A method for measuring a stability of a static random access memory (SRAM) cell in an integrated circuit (IC) device, comprising:
measuring a voltage transfer curve from a first side of a test structure, wherein the first side of the test structure is electrically coupled to a first internal node of the SRAM cell on a first side of a cut off via a first transmission gate (TG);
obtaining a butterfly curve by plotting a curve that is substantially symmetrical to the measured voltage transfer curve; and
determining a static noise margin (SNM) for each of the one or more SRAM cells by measuring an area bounded by the butterfly curve, wherein:
the cut off provides an electrical open between the first side of the cut off and a second side of the cut off; and
the first internal node is electrically coupled to a first external pin through the first TG; and
a second internal node at the second side of the cut off is electrically coupled to a second external pin through a second TG.

### Claim 10 (depends on 9)

The method of claim 9, wherein the IC device is fabricated in a complementary metal-oxide-semiconductor (CMOS) process.

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
measuring a plurality of SRAM cells using a plurality of SRAM SNM test structures to provide a family of voltage transfer curves;
statistically sampling distributions of the family of voltage transfer curves;
deriving a butterfly curve from the statistically sampled distributions of the family of voltage transfer curves; and
determining a static noise margin (SNM) for the plurality of SRAM cells by measuring an area bounded by the derived butterfly curve.

### Claim 12 (depends on 9)

The method of claim 9, further comprising, populating one column of a table of SNM measurements based on measurements obtained from a left side of the cut off of the SRAM cell, and populating another column of the table of SNM measurements based on measurements obtained from a right side of the cut off of the SRAM cell.

### Claim 13 (depends on 9)

The method of claim 9, wherein the first TG, the second TG, and the SRAM cell each comprise a same type of transistor.

### Claim 14 (depends on 9)

The method of claim 9, further comprising calibrating a voltage drop in measurement circuitry of the test structure, wherein calibrating the voltage drop includes:
using a word line (WL) decoder and column multiplexer peripheral circuitry of the SRAM cell; and
forming connecting wires that electrically couple the first TG to the second TG.

### Claim 15 (depends on 9)

The method of claim 9, wherein feedback between the first internal node and the second internal node is broken at the cut off.

### Claim 16

An array of test structures comprising a plurality of test structures for directly measuring a stability of a plurality of static random access memory (SRAM) cells, the array of test structures comprising:
multiple levels of transmission gates (TGs);
a first chip analog input/output (IO); and
a second chip analog IO, wherein:
a plurality of internal nodes of the plurality of SRAM cells are electrically coupled through the multiple levels of transmission gates (TGs) to one of the first chip analog IO and the second chip analog IO; and
each test structure of the plurality of test structures is operable to address a respective one of the plurality of SRAM cells, and wherein each test structure of the plurality of test structures are operable to measure static noise margin (SNM) of a respective one of the plurality of SRAM cells.

### Claim 17 (depends on 16)

The array of test structures of claim 16, wherein each test structure of the plurality of test structures comprises, for an SRAM cell of the plurality SRAM cells:
a first transmission gate (TG) electrically coupled to a first side of a cut off in the SRAM cell;
a second TG electrically coupled to a second side of the cut off; and
a first external pin electrically coupled to the first TG and a second external pin electrically coupled to the second TG, wherein:
feedback between the internal nodes of the SRAM cell is broken at the cut off;
a first internal node of the plurality of internal nodes is electrically coupled to the first external pin through the first TG; and
a second internal node of the plurality of internal nodes is electrically coupled to the second external pin through the second TG.

### Claim 18 (depends on 16)

The array of test structures of claim 16, wherein the plurality of internal nodes of the plurality of SRAM cells include calibration (CAL) cells.

### Claim 19 (depends on 16)

The array of test structures of claim 16, wherein the plurality of SRAM cells include 6-cell SRAM cells.

### Claim 20 (depends on 16)

The array of test structures of claim 16, wherein the plurality of SRAM cells include 7-cell SRAM cells.

### Claim 21 (depends on 16)

The array of test structures of claim 16, wherein the plurality of SRAM cells include 8-cell SRAM cells.

### Claim 22 (depends on 16)

The array of test structures of claim 16, wherein the plurality of SRAM cells include Dual Interlocked Cell (DICE) SRAM cells.