# US 11,029,216 B1 · IC with stragically biased digital circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,029,216 B1 - Document ID: US11029216B1 - Status: Granted - Kind: B1 - Application number: 16/528,496 - Filed: 2019-07-31 - Granted: 2021-06-08 - Earliest claimed: 2016-10-27 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Thomas Vogelsang; Frederick A. Ware - Web page: https://patentgrep.com/patent/US11029216B1 ## CPC - G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) - G05F 1/562: {with a threshold detection shunting the control path of the final control device} - G05F 3/245: {producing a voltage or current as a predetermined function of the temperature} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 84/0191: {Manufacturing their doped wells} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage. ## Claims ### Claim 1 A method of operating an integrated-circuit (IC) component, the method comprising: applying a first bias voltage to a first substrate region disposed adjacent a first plurality of transistors to effect a leakage current for the first plurality of transistors below a nominal leakage current; and applying a second bias voltage, different from the first bias voltage, to a second substrate region disposed adjacent a second plurality of transistors to effect a switching speed for the second plurality of transistors greater than a nominal switching speed. ### Claim 2 (depends on 1) The method of claim 1 wherein applying the first and second bias voltages comprises applying the first and second bias voltages during operation of the IC component at a cryogenic temperature. ### Claim 3 (depends on 2) The method of claim 2 further comprising applying third and fourth voltages to the first and second substrate regions, respectively, during operation of the IC component at a test environment temperature substantially higher than the cryogenic temperature. ### Claim 4 (depends on 2) The method of claim 2 further comprising generating the first, second, third and fourth bias voltages and supplying the first, second, third and fourth bias voltages to a selector circuit that outputs, to the first and second substrate regions, either the first and second bias voltages or the third and fourth bias voltages according to whether a control signal is in a first state or a second state. ### Claim 5 (depends on 4) The method of claim 4 further comprising receiving the control signal from a source external to the IC component. ### Claim 6 (depends on 4) The method of claim 4 further comprising generating the control signal in either the first state or the second state according to whether a temperature detection circuit of the IC component detects a temperature below or above a threshold temperature, respectively. ### Claim 7 (depends on 6) The method of claim 6 wherein the threshold temperature corresponds to a temperature not higher than 100 Kelvin. ### Claim 8 (depends on 1) The method of claim 1 wherein the first plurality of transistors comprises a first plurality of N-type metal-oxide-semiconductor (NMOS) transistors and the second plurality of transistors comprises a second plurality of NMOS transistors, the method further comprising: applying a third bias voltage to a third substrate region disposed adjacent a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors to effect a leakage current for the first plurality of PMOS transistors below the nominal leakage current; and applying a fourth bias voltage to a fourth substrate region disposed adjacent a second plurality of PMOS transistors to effect a switching speed for the second plurality of PMOS transistors greater than the nominal switching speed. ### Claim 9 (depends on 8) The method of claim 8 wherein applying the first, second, third and fourth bias voltages comprises applying the first, second, third and fourth bias voltages during operation of the IC component at a cryogenic temperature, the method further comprising applying fifth, sixth, seventh and eighth bias voltages to the first, second, third and fourth substrate regions, respectively, during operation of the IC component at a test environment temperature substantially higher than the cryogenic temperature. ### Claim 10 (depends on 1) The method of claim 1 wherein the first and second substrate regions and the first and second pluralities of transistors are implemented in a low-threshold-voltage silicon-on-insulator process in which the first and second substrate regions are separated from the first and second pluralities of transistors, respectively, by a buried oxide. ### Claim 11 (depends on 1) The method of claim 1 further comprising applying a third bias voltage, different from the first and second bias voltages, to a third substrate region disposed adjacent a third plurality of transistors. ### Claim 12 An integrated-circuit (IC) component comprising: first and second pluralities of transistors; first and second substrate regions disposed adjacent the first plurality of transistors and the second plurality of transistors, respectively; and biasing circuitry to apply (i) a first bias voltage to the first substrate region to effect a leakage current for the first plurality of transistors below a nominal leakage current and (ii) a second bias voltage, different from the first bias voltage, to the second substrate region to effect a switching speed for the second plurality of transistors greater than a nominal switching speed. ### Claim 13 (depends on 12) The IC component of claim 12 wherein the biasing circuitry to apply the first and second bias voltages comprises circuitry to apply the first and second bias voltages to the first and second substrate regions during operation of the IC component at a cryogenic temperature and to apply third and fourth voltages to the first and second substrate regions, respectively, during operation of the IC component at a test environment temperature substantially higher than the cryogenic temperature. ### Claim 14 (depends on 13) The IC component of claim 13 wherein the biasing circuitry comprises a bias voltage generator to generate the first, second, third and fourth bias voltages, and wherein the circuitry to apply the first and second bias voltages to the first and second substrate regions during operation of the IC component at a cryogenic temperature and to apply the third and fourth voltages to the first and second substrate regions during operation of the IC component at a test environment temperature substantially higher than the cryogenic temperature comprises selector circuitry coupled to receive the first, second, third and fourth bias voltages from the bias voltage generator and to output, to the first and second substrate regions, either the first and second bias voltages or the third and fourth bias voltages according to whether a control signal is in a first state or a second state. ### Claim 15 (depends on 14) The IC component of claim 14 further comprising a temperature detection circuit to generate the control signal in either the first state or the second state according to detected temperature. ### Claim 16 (depends on 12) The IC component of claim 12 wherein the first plurality of transistors comprises a first plurality of N-type metal-oxide-semiconductor (NMOS) transistors and the second plurality of transistors comprises a second plurality of NMOS transistors, and wherein the IC component further comprises: first and second pluralities of P-type metal-oxide-semiconductor (PMOS) transistors; third and fourth substrate regions disposed adjacent the first plurality of PMOS transistors and the second plurality of PMOS transistors, respectively; and wherein the biasing circuitry is further to apply: a third bias voltage to the third substrate region to effect a leakage current for the first plurality of PMOS transistors below the nominal leakage current; and a fourth bias voltage to the fourth substrate region to effect a switching speed for the second plurality of PMOS transistors greater than the nominal switching speed. ### Claim 17 (depends on 16) The IC component of claim 16 wherein the temperature detection circuit generates the control signal in either the first state or the second state according to whether the detected temperature exceeds a temperature threshold, the temperature threshold corresponding to a temperature not higher than 100 Kelvin. ### Claim 18 (depends on 12) The IC component of claim 12 wherein the first and second substrate regions comprise doped wells separated from the first and second pluralities of transistors, respectively, by a buried oxide within a low-threshold-voltage silicon-on-insulator substrate. ### Claim 19 (depends on 18) The IC component of claim 18 wherein the biasing circuitry to apply the first, second, third and fourth bias voltages comprises circuitry to apply the first, second, third and fourth bias voltages during operation of the IC component at a cryogenic temperature, and to apply fifth, sixth, seventh and eighth bias voltages to the first, second, third and fourth substrate regions, respectively, during operation of the IC component at a test environment temperature substantially higher than the cryogenic temperature. ### Claim 20 An integrated-circuit (IC) component comprising: first and second pluralities of transistors; first and second substrate regions disposed adjacent the first plurality of transistors and the second plurality of transistors, respectively; and means for applying (i) a first bias voltage to the first substrate region to effect a leakage current for the first plurality of transistors below a nominal leakage current and (ii) a second bias voltage, different from the first bias voltage, to the second substrate region to effect a switching speed for the second plurality of transistors greater than a nominal switching speed.